PPM L1 State - 1.0 English

Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343)

Document ID
PG343
Release Date
2024-05-30
Version
1.0 English

These steps outline the transition of the core to the PPM L1 state:

  1. The transition to a lower power PPM L1 state is always initiated by an upstream device, by programming the PCI Express® device power state to D3-hot (or to D1 or D2, if they are supported).
  2. The device power state is communicated to the user logic through the cfg_function_power_state output.
  3. The core throttles/stalls the user logic from initiating any new transactions on the user interface by deasserting s_axis_rq_tready. Any pending transactions on the user interface are, however, accepted fully and can be completed later.
    • The core is configured as an Endpoint and the User Configuration Space is enabled. In this situation, the user application must refrain from sending new Request TLPs if cfg_function_power_state indicates non-D0, but the user application can return Completions to Configuration transactions targeting User Configuration space.
    • The core is configured as a Root Port. To be compliant in this situation, the user application should refrain from sending new Requests if cfg_function_power_state indicates non-D0.
  4. The core exchanges appropriate power management DLLPs with its link partner to successfully transition the link to a lower power PPM L1 state. This action is transparent to the user logic.
  5. All user transactions are stalled for the duration of time when the device power state is non-D0, with the exceptions indicated in step 3.