Limitations - 1.0 English

Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343)

Document ID
PG343
Release Date
2024-05-30
Version
1.0 English

Speed Change Related Issue

Description
Repeated speed changes can result in the link not coming up to the intended targeted speed.
Workaround
A follow-on attempt should bring the link back. In extremely rare scenarios, a full reboot might be required.

Link Autonomous Bandwidth Status (LABS) Bit

Description
As a Root Complex when performing the link width/rate changes, the link width change works as expected. However, the PCIe protocol requires a LABS bit which is not getting set after the link width/rate change.
Note: This is an informational bit and does not impact actual functionality.
Workaround
Ensure the software / application ignores the LABS bit as this is an informational bit and does not impact functionality.
Note: For any application, AMD recommends that you make sure the link is quiesced and no transactions are pending before performing any link rate changes.

AXI Bridge

  1. For this subsystem, the bridge master and bridge slave cannot achieve more than 128 Gbps.
  2. Bridge is compliant with all MPS and MRRS settings; however, the traffic initiated from the Bridge is limited to 256 Bytes (max).
  3. AXI address width is limited to 48 bits.

PCIe Transaction Type

The PCIe® transactions generated are those that are compatible with the AXI4 specification. The following table lists the supported PCIe transaction types.

Table 1. Supported PCIe Transaction Types
TX RX
MRd32 MRd32
MRd64 MRd64
MWr32 MWr32
MWr64 MWr64
Msg Msg
Cpl Cpl
CplD CplD
Cfg Type0/1 (For Root Port)  

AXI Slave

  • Only supports the INCR burst type. Other types result in the Slave Illegal Burst (SIB) interrupt.
  • No memory type support (AxCACHE)
  • No protection type support (AxPROT)
  • No lock type support (AxLOCK)
  • No non-contiguous byte enable support (WSTRB)

AXI Master

  • Only issues the INCR burst type
  • Only issues the data, non-secure, and unprivileged protection type

Power Management - ASPM L1/L0s/PM D3

Description
  1. Enabling ASPM L0s / ASPM L1 could show correctable errors being reported on the link by both link partners (that is; replay timer timeout, replay timer rollover, receiver error).
  2. A PCIe Endpoint device might also log errors when Configuration PM D3 transition request comes in during non-quiesced traffic mode.
  3. A PCIe Root Port device does not support ASPM L1 or L0s.
Workaround
  1. It is recommended that the application disables correctable error reporting or ignores correctable errors reported in event of link transitioned to ASPM L0s / ASPM L1.
  2. For transition to D3Hot, software needs to make sure that the link is quiesced. To ensure Memory Write packets are finished, issue a Memory Read request to the same location. When the completion packet is received, it indicates that the link is quiesced and PM D3 request can be issued.
Note: This limitation apply to both CPM4 and CPM5 devices.

APB3 Simulation Support

  • There is no support for APB3 simulation.

Power Management - ASPM L1/L0s

  • A PCIe Root Port device does not support ASPM L1 or L0s.

Completion Timeout Ranges

  • The PCIe core advertises completion timeout range BC, but ranges B2, C1, and C2 (specified in the device control 2 register) are not supported and they lead to early timeouts if the host attempts to use them.

Loopback Behavior in RP Mode

Description
In an extremely rare scenario in Rootport applications under marginal link quality conditions, the link enters into loopback.slave state during link training when there are 2 TS1s with loopback bit set seen in the below order and not just when 2 consecutive TS1s are received.
  • TS1 with loopback bit set
  • BAD TS1 (parity error)
  • BAD TS1
  • BAD TS1
  • TS1 with loopback bit set
If there is a good TS1 with loopback bit not set in between the 2 TS1s with loopback bit set, then the IP does not enter loopback.slave state.
Workaround
Ensure that the link quality on both sides meet or exceed requirements of the PCI Express Base Specification and PCI Express Card Electromechanical Specification so that there are no BAD TS1s. In a rare event of linkup failure, a follow-on link training attempt should bring the link up.