TX Data Signals - 1.0 English

Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343)

Document ID
PG343
Release Date
2024-05-30
Version
1.0 English
Table 1. TX Data Signals
Name I/O Width Description
phy_txdata[63:0] O 64 Parallel data output. Bits [63:32] are used for Gen4 only and must be ignored in Gen1, Gen2, and Gen3. Bits [31:16] are used for Gen3 only and must be ignored in Gen1 and Gen2. Per lane.
phy_txdatak[1:0] O 2 Indicates whether TXDATA is control or data for Gen1 and Gen2 only. Per lane.
  • 0b: Data
  • 1b: Control
phy_txdata_valid O 1 This signal allows the MAC to instruct the PHY to ignore TXDATA for one PCLK cycle. When High, this indicates that the PHY is to use TXDATA. When Low, this indicates the PHY is notto use TXDATA for one PCLK cycle. Gen3 and Gen4 only. Per lane.
phy_txstart_block O 1 This signal allows the MAC to tell the PHY the starting byte for a 128b block. The starting byte for a 128b block must always start at bit [0] of TXDATA. Gen3 and Gen4 only. Per lane.
phy_txsync_header[1:0] O 2 Provide the sync header for the PHY to use the next 130b block. The PHY reads this value when the txsync_block is asserted. Gen3 and Gen4 only. Per lane.