Required Constraints - 1.0 English

Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343)

Document ID
PG343
Release Date
2024-05-30
Version
1.0 English

The Versal™ Adaptive SoC Integrated Block for PCI Express® solution requires the specification of timing and other physical implementation constraints to meet specified performance requirements for PCI Express® . These constraints are provided with the Endpoint and Root Port solutions in a Xilinx Design Constraints (XDC) file. Pinouts and hierarchy names in the generated XDC correspond to the provided example design.

Important: If the example design top file is not used, copy the IBUFDS_GTE instance for the reference clock, IBUF Instance for sys_rst and also the location and timing constraints associated with them into your local design top. In addition, the GT location constraints need to be added in top-level xdc. For more information, see the GT Location in GT Selection and Pin Planning appendix.

To achieve consistent implementation results, an XDC containing these original, unmodified constraints must be used when a design is run through the AMD tools. For additional details on the definition and use of an XDC or specific constraints, see Vivado Design Suite User Guide: Using Constraints (UG903).

Constraints provided with the integrated block solution is tested in hardware and provide consistent results. Constraints can be modified, but modifications should only be made with a thorough understanding of the effect of each constraint. Additionally, support is not provided for designs that deviate from the provided constraints.