Clock and Reset Interface - 1.0 English

Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343)

Document ID
PG343
Release Date
2024-05-30
Version
1.0 English

Fundamental to the operation of the core, the Clock and Reset interface provides the system-level clock and reset to the core along with the user application clock and reset signal. The following table defines the ports in the Clock and Reset interface of the core.

The user_clk signal is the derived clock from the TXOUTCLK pin which is the output from the GT Wizard IP. TXOUTCLK is dependent on the pmareset, progdivreset, and txpisopd signals, and also on sys_clk or refclk which is connected to GT Wizard IP. So, user_clk is not expected to run continuously. For more details about TXOUTCLK, refer the corresponding GT Wizard documents.

Table 1. Clock and Reset Interface Port Descriptions
Port I/O Width Description
user_clk O 1 User clock output (62.5, 125, or 250 MHz)

This clock has a fixed frequency and is configured in the AMD Vivado™ Integrated Design Environment (IDE).

user_reset O 1 This signal is deasserted synchronously with respect to user_clk. It is deasserted and asserted asynchronously with sys_reset assertion. This signal is asserted for core in-band reset events such as Hot Reset or Link Disable.
sys_clk I 1 Reference clock

This clock has a selectable frequency of 100 MHz,125 MHz and 250 MHz.

sys_clk_gt I 1 PCIe reference clock for GT. This clock must be driven directly from IBUFDS_GTE (same definition and frequency as sys_clk). This clock has a selectable frequency of 100 MHz, 125 MHz and 250 MHz, which is the same as in sys_clk.
sys_reset I 1 Fundamental reset input to the core (asynchronous)

This input is active-Low by default to match the PCIe edge connector reset polarity.

phy_rdy_out O 1 The phy ready signal indicates that the GT Wizard is ready. This signal is driven by phy_rst FSM on receiving the phy status from the GT Wizard core.

The PL PCIE4 does not have dedicated reset pin routing.