This IP can support two example designs in Endpoint configuration. One is Programmed Input/Output (PIO) example design and other one is Bus Master DMA (BMD) example design.
The example simulation design for the Endpoint configuration of the integrated block consists of two discrete parts:
- The Root Port Model, a test bench that generates, consumes, and checks PCI Express® bus traffic.
- The Programmed Input/Output (PIO) example design, a completer application for PCI Express. The PIO example design responds to Read and Write requests to its memory space and can be synthesized for testing in hardware.
Note:
Not all modes have example design support, for example, Straddle,
Address aligned mode, SRIOV, MSI-X, and MSI.
Note:
Currently, the BMD design is the default example design. For details about the BMD
design, see the Bus Master Performance Demonstration Reference
Design for the Xilinx Endpoint PCI Express Solutions (XAPP1052). To use the PIO design, enter the
command below at the Vivado Tcl Console prompt after the Versal Adaptive SoC Integrated Block for PCIe® IP is generated. Example design is provided for reference
only and should not be used in a production design without extensive testing and
verification.
set_property config.bmd_pio_mode false [get_ips pcie_versal_0]