Port Updates - 1.0 English

Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343)

Document ID
PG343
Release Date
2024-05-30
Version
1.0 English
Table 1. Port Width Changes between UltraScale Integrated Block and Versal Integrated Block Cores
Name I/O UltraScale+ Width Versal PCIe Width Notes
pcie_rq_tag0 O 8 10 For details, see Table 2.
pcie_rq_tag1 O 8 10
pcie0_s_axis_cq_tuser O 183 229
pcie0_s_axis_rq_tuser O 137 183 For details, see Table 2.