Expectation Tasks - 1.0 English

Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343)

Document ID
PG343
Release Date
2024-05-30
Version
1.0 English
Table 1. Expectation Tasks
Name Input(s) Output Description
TSK_EXPECT_CPLD

traffic_class

td

ep

attr

length

completer_id

completer_status

bcm

byte_count

requester_id

tag

address_low

2:0

-

-

1:0

10:0

15:0

2:0

-

11:0

15:0

7:0

6:0

Expect status

Waits for a Completion with Data TLP that matches traffic_class, td, ep, attr, length, and payload.

Returns a 1 on successful completion; 0 otherwise.

TSK_EXPECT_CPL

traffic_class

td

ep

attr

completer_id

completer_status

bcm

byte_count

requester_id

tag

address_low

2:0

-

-

1:0

15:0

2:0

-

11:0

15:0

7:0

6:0

Expect status

Waits for a Completion without Data TLP that matches traffic_class, td, ep, attr, and length.

Returns a 1 on successful completion; 0 otherwise.

TSK_EXPECT_MEMRD

traffic_class

td

ep

attr

length

requester_id

tag

last_dw_be

first_dw_be

address

2:0

-

-

1:0

10:0

15:0

7:0

3:0

3:0

29:0

Expect status

Waits for a 32-bit Address Memory Read TLP with matching header fields.

Returns a 1 on successful completion; 0 otherwise. This task can only be used in conjunction with Bus Master designs.

TSK_EXPECT_MEMRD64

traffic_class

td

ep

attr

length

requester_id

tag

last_dw_be

first_dw_be

address

2:0

-

-

1:0

10:0

15:0

7:0

3:0

3:0

61:0

Expect status

Waits for a 64-bit Address Memory Read TLP with matching header fields. Returns a 1 on successful completion; 0 otherwise.

This task can only be used in conjunction with Bus Master designs.

TSK_EXPECT_MEMWR

traffic_class

td

ep

attr

length

requester_id

tag

last_dw_be

first_dw_be

address

2:0

-

-

1:0

10:0

15:0

7:0

3:0

3:0

29:0

Expect status

Waits for a 32-bit Address Memory Write TLP with matching header fields. Returns a 1 on successful completion; 0 otherwise.

This task can only be used in conjunction with Bus Master designs.

TSK_EXPECT_MEMWR64

traffic_class

td

ep

attr

length

requester_id

tag

last_dw_be

first_dw_be

address

2:0

-

-

1:0

10:0

15:0

7:0

3:0

3:0

61:0

Expect status

Waits for a 64-bit Address Memory Write TLP with matching header fields. Returns a 1 on successful completion; 0 otherwise.

This task can only be used in conjunction with Bus Master designs.

TSK_EXPECT_IOWR

td

ep

requester_id

tag

first_dw_be

address

data

-

-

15:0

7:0

3:0

31:0

31:0

Expect status

Waits for an I/O Write TLP with matching header fields. Returns a 1 on successful completion; 0 otherwise.

This task can only be used in conjunction with Bus Master designs.