PCIe Link Debug Enablement - 1.0 English

Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343)

Document ID
PG343
Release Date
2024-05-30
Version
1.0 English

The Versal™ Adaptive SoC Integrated Block for PCI Express® customization provides an option to enable PCIe® Link Debug. Enabling this option inserts a debug core inside the IP core that recognizes by the AMD Vivado™ Hardware Manager and provide PCIe specific debug information and view. The debug view provides information relating to the current link speed, current link width, and LTSSM state transitions, which can facilitate debug of PCIe link related issues.

Note: This appendix provides guidance for both CPM and PL PCIe based solutions. For this core, the PL PCIe related guidance is of primary importance, while the CPM related guidance might be relevant and is provided for informational purposes.