Clock and Reset Signals

Clock and Reset Signals - 1.0 English

Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343)

Document ID

PG343

Release Date

2024-11-22

Version

1.0 English

Table 1. Clock and Reset Signals
Name	I/O	Width	Clock Domain	Description
phy_coreclk	I	1	coreclk	Core clock options: 250 MHz 500 MHz
phy_userclk	I	1	userclk	User clock options: 62.5 MHz 125 MHz 250 MHz phy_userclk is edge aligned and phase aligned to phy_coreclk.
phy_pclk	I	1	pclk	PIPE interface clock options: 125 MHz: Gen1 operating speed 250 MHz: Gen2, Gen3, Gen4 operating speed 500 MHz: Gen4 operating speed phy_pclk is edge aligned, but not phase aligned, to phy_coreclk and phy_userclk.