WIRE - 2024.1 English

Vivado Design Suite Properties Reference Guide (UG912)

Document ID
UG912
Release Date
2024-05-30
Version
2024.1 English

Description

A WIRE is a device object used for routing connections, or NETs, on the AMD part. A WIRE is a strip of interconnect metal inside a single tile. Wires connect between PIPs, tie-offs, and SITE_PINs.

Tip: The WIRE object should not be confused with the wire entity in the Verilog files of a design. Those wires are related to NETs in the design rather than the routing resources of the device which are defined by the WIRE object.
Figure 1. WIRE Objects

Related Objects

As seen in the above figure, WIRE objects are related to TILEs, NODEs, PIPs, or NETs. You can query WIREs using a form of the following Tcl command:

get_wires -of [get_tiles INT_R_X7Y47]

You can also query the TILEs that WIREs are located in; or the NODEs and PIPs associated with specific WIREs:

get_nodes -of_objects [get_wires INT_R_X7Y47/NW6BEG1]

Properties

The properties on a WIRE object can be reported with a command such as the following:

report_property -all [lindex [get_wires -of [get_nodes INT_R_X7Y47/NW6BEG1]] 0]
Tip: Due to the number of WIREs on a device, using the get_wires Tcl command without -of_objects or -filters to narrow the results is not recommended.

The properties include the following, with example values:

Property	Type	Read-only	Visible	Value
CLASS	string	true	true	wire
COST_CODE	int	true	true	3
ID_IN_TILE_TYPE	int	true	true	123
IS_CONNECTED	bool	true	true	1
IS_INPUT_PIN	bool	true	true	0
IS_OUTPUT_PIN	bool	true	true	0
IS_PART_OF_BUS	bool	true	true	0
NAME	string	true	true	INT_R_X7Y47/NW6BEG1
NUM_DOWNHILL_PIPS	int	true	true	0
NUM_INTERSECTS	int	true	true	1
NUM_PIPS	int	true	true	20
NUM_TILE_PORTS	int	true	true	0
NUM_UPHILL_PIPS	int	true	true	20
SPEED_INDEX	int	true	true	2232
TILE_NAME	string	true	true	INT_R_X7Y47
TILE_PATTERN_OFFSET	int	true	true	0