LOC - 2024.2 English - UG912

LOC specifies the placement assignment of a logic cell to the SITE resources of the target AMD part.

The LOC property or constraint is sometimes used with the BEL property to define the exact placement of cells within the device. In these cases the BEL constraint must be defined before the LOC constraint, or a placement error will occur.

Architecture Support

All architectures.

Applicable Objects

Cells (get_cells): Any primitive cell

Values

Site name (for example, SLICE_X15Y14 or RAMB18_X6Y9)

Syntax

Verilog Syntax

Place the Verilog attribute immediately before the instantiation of a component.

Tip: The Verilog attribute can also be placed before the reg declaration of an inferred register, SRL, or LUTRAM when that reg can be placed into a single device site:

(* LOC = "site_name" *)
// Designates placed_reg to be placed in SLICE site SLICE_X0Y0 
(* LOC = "SLICE_X0Y0" *) reg placed_reg;

VHDL Syntax

Declare the VHDL attribute as follows:

attribute LOC : string;

For an instantiated instance, specify the VHDL attribute as follows:

attribute LOC of instance_name : label is "site_name";

Where instance_name is the instance name of an instantiated primitive.

VHDL Syntax Example:

-- Designates instantiated register instance placed_reg to be placed
--	in SLICE site SLICE_X0Y0
attribute LOC of placed_reg : label is "SLICE_X0Y0";

For an inferred instance, specify the VHDL attribute as follows:

attribute LOC of signal_name : signal is "site_name";

Where signal_name is the signal name of an inferred primitive that can be placed into a single site.

VHDL Syntax Example:

-- Designates inferred register placed_reg to be placed in SLICE site SLICE_X0Y0 
attribute LOC of placed_reg : signal is "SLICE_X0Y0";

XDC Syntax

set_property LOC site_name [get_cells instance_name]

Where instance_name is a primitive instance.

XDC Syntax Example:

# Designates placed_reg to be placed in SLICE site SLICE_X0Y0 
set_property LOC SLICE_X0Y0 [get_cells placed_reg]

Affected Steps

• Design Floorplanning
• Place Design