IOSTANDARD - 2024.1 English

Vivado Design Suite Properties Reference Guide (UG912)

Document ID
UG912
Release Date
2024-06-05
Version
2024.1 English

IOSTANDARD specifies which programmable I/O Standard to use to configure input, output, or bidirectional ports on the target device.

Important: You must explicitly define an IOSTANDARD on all ports in an I/O Bank before Vivado Design Suite will create a bitstream from the design. However, IOSTANDARDs cannot be applied to GTs or XADCs.

You can mix different IOSTANDARDs in a single I/O Bank, however, the IOSTANDARDs must be compatible. The following rules must be followed when combining different input, output, and bidirectional I/O standards in a single I/O bank:

  1. Output standards with the same output VCCO requirement can be combined in the same bank.
  2. Input standards with the same VCCO and VREF requirements can be combined in the same bank.
  3. Input standards and output standards with the same VCCO requirement can be combined in the same bank.
  4. When combining bidirectional I/O with other standards, make sure the bidirectional standard can meet the first three rules.
Architecture Support
All architectures.
Applicable Objects
  • Ports (get_ports)
    • Any port - Define the IOSTANDARD in the RTL source of I/O Ports, or as XDC constraints for port cells.
Values
There are many different valid I/O Standards for the target AMD FPGA. Refer to the 7 Series FPGAs SelectIO Resources User Guide (UG471) and the UltraScale Architecture SelectIO Resources User Guide (UG571) for device specific IOSTANDARD values.

Syntax

Verilog Syntax

To set this parameter, place the proper Verilog syntax before the top-level port declaration.

(* IOSTANDARD = "value" *)

Verilog Syntax Example:

// Sets the I/O Standard on the STATUS output to LVCMOS12 
(* IOSTANDARD = "LVCMOS12" *) output STATUS,
VHDL Syntax

Place the proper VHDL attribute syntax before the top-level port declaration. Declare and specify the VHDL attribute as follows:

attribute IOSTANDARD : string;
attribute IOSTANDARD of <port_name>: signal is "<standard>";

Where port_name is a top-level port.

VHDL Syntax Example:

STATUS : out std_logic; 
attribute IOSTANDARD : string;
-- Sets the I/O Standard on the STATUS output to LVCMOS12 attribute IOSTANDARD of STATUS: signal is "LVCMOS12";
XDC Syntax

The IOSTANDARD can also be defined as an XDC constraint on port objects in the design.

set_property IOSTANDARD value [get_ports port_name]

Where port_name is a top-level port.

XDC Example Syntax:

# Sets the I/O Standard on the STATUS output to LVCMOS12 
set_property IOSTANDARD LVCMOS12 [get_ports STATUS]

Affected Steps

  • I/O Planning
  • Report Noise
  • Report Power
  • Report DRC
  • Place Design

See Also

Refer to the following design elements in the Vivado Design Suite 7 Series FPGA and Zynq 7000 SoC Libraries Guide (UG953), or the UltraScale Architecture Libraries Guide (UG974):

  • OBUF
  • OBUFT
  • IOBUF