IS_SOFT - 2024.1 English

Vivado Design Suite Properties Reference Guide (UG912)

Document ID
UG912
Release Date
2024-05-30
Version
2024.1 English

This is a Pblock property that indicates whether the Pblock must strictly be obeyed.

When the IS_SOFT property is set to TRUE, Pblocks are ignored starting with physical synthesis in placer through the end of the implementation flow. This approach is particularly helpful for preserving the overall placement while giving additional flexibility to placement algorithms that reduce congestion, move logic closer to optimal locations, and increase the efficiency of physical optimizations.

Restrictions: If a Pblock defines a Dynamic Function eXchange (DFX) dynamic region, then IS_SOFT TRUE is ignored to prevent DRC failures.

Architecture Support
All architectures.
Applicable Objects
Pblocks (get_pblocks)
Values
  • TRUE: Pblock used for initial placement, then assigned leaf cells are allowed to move outside Pblock boundaries to improve timing. This is default.
  • FALSE: Pblock boundaries are hard and must be obeyed throughout the flow.

Syntax

Verilog Syntax

Not applicable

VHDL Syntax

Not applicable

XDC Syntax
set_property IS_SOFT <TRUE | FALSE> [get_pblocks <pblock_name>]

Where <pblock_name> specifies the PBlock or PBlocks to apply the property to.

XDC Example:

set_property IS_SOFT TRUE [get_pblocks pblock_0]

Affected Steps

  • Place Design
  • Phys Opt Design