This attribute can be set in both the RTL and in the XDC.
The Vivado synthesis tool supports
extraction of Finite State Machines (FSM) in a variety of configurations as
determined by the FSM_ENCODING property, or the -fsm_extraction command line option for Vivado synthesis. Refer to the
Vivado
Design Suite User Guide: Synthesis (UG901) for more information.
A state machine can enter into an invalid, or “unreachable” state that causes the design to fail. FSM_SAFE_STATE tells synthesis to insert logic into the state machine that detects if there is an invalid state and then puts it into a known state on the next clock cycle. If an FSM enters an invalid state, the FSM_SAFE_STATE property defines a recovery state for use when an FSM is synthesized in the Vivado synthesis tool.
- Architecture Support
- All architectures.
- Applicable Objects
- State machine registers.
- Values
-
-
reset_state: Return the state machine to the RESET state, as determined by the Vivado synthesis tool. -
power_on_state: Return the state machine to the POWER_ON state, as determined by the Vivado synthesis tool. -
default_state: Return the state machine to the default state, as defined by the state machine; even if that state is unreachable, using Hamming-2 encoding detection for one bit/flip. -
auto_safe_state: implies Hamming-3 encoding.
-
Syntax
- Verilog Syntax
-
(* fsm_safe_state = "reset_state" *) reg [2:0] state; (* fsm_safe_state = "reset_state" *) reg [7:0] my_state; - VHDL Syntax
-
type count_state is (zero, one, two, three, four, five, six, seven); signal my_state : count_state; attribute fsm_safe_state : string; attribute fsm_safe_state of my_state : signal is "power_on_state"; - XDC Syntax
-
set_property fsm_safe_state reset_state [get_cells state_reg*]
Affected Steps
- Synthesis