PACKAGE_PIN defines a specific assignment, or placement, of a top-level port in the logical design to a physical package pin on the device.
Recommended: To assign I/O ports to physical pins on
the device package, use the PACKAGE_PIN property rather than LOCS. Use the LOC
property to assign logic cells to device resources on the target AMD FPGA.
- Architecture Support
- All architectures.
- Applicable Objects
- Ports (
get_ports): Any top-level port. - Values
- Package pin name.
Syntax
- Verilog Syntax
-
Place the Verilog attribute immediately before the port declaration:
(* PACKAGE_PIN = "pin_name" *)Verilog Syntax Example
// Designates port CLK to be placed on pin B26 (* PACKAGE_PIN = "B26" *) input CLK; - VHDL Syntax
-
Declare the VHDL attribute as follows:
attribute PACKAGE_PIN : string;Specify the VHDL attribute as follows:
attribute PACKAGE_PIN of port_name : signal is "pin_name";VHDL Syntax Example:
-- Designates CLK to be placed on pin B26 attribute PACKAGE_PIN of CLK : signal is "B26"; - XDC Syntax
-
set_property PACKAGE_PIN pin_name [get_ports port_name]XDC Syntax Example
# Designates CLK to be placed on pin B26 set_property PACKAGE_PIN B26 [get_ports CLK]
Affected Steps
- Pin planning
- Place Design