KEEP - 2024.1 English

Vivado Design Suite Properties Reference Guide (UG912)

Document ID
UG912
Release Date
2024-05-30
Version
2024.1 English

Use the KEEP attribute to prevent optimizations. Where signals are optimized or absorbed into logic blocks, the KEEP attribute instructs the synthesis tool to keep the signal it was placed on, and extract that signal to the netlist.

For example, if a signal is an output of a 2-bit AND gate, and it drives another AND gate, the KEEP attribute can be used to prevent that signal from being merged into a larger LUT that encompasses both AND gates.

KEEP is also commonly used in conjunction with timing constraints. If there is a timing constraint on a signal that would normally be optimized, KEEP prevents that and allows the correct timing rules to be used.

However, you should use care not to put KEEP on signals that do not drive anything. Synthesis will preserve those signals, and they can cause problems in downstream processes.

Note: KEEP is not supported on the port of a module or entity. If specific ports are needed to be kept, either use the flatten_hierarchy = “none” setting, or put a DONT_TOUCH on the module or entity itself.
CAUTION:
Be careful when using KEEP with other attributes. In cases where other attributes are in conflict with KEEP, the KEEP attribute usually takes precedence.

Examples:

  • When you have a MAX_FANOUT attribute on one signal and a KEEP attribute on a second signal that is driven by the first; the KEEP attribute on the second signal would not allow fanout replication.
  • With a RAM STYLE=”block”, when there is a KEEP on the register that would need to become part of the RAM, the KEEP attribute prevents the block RAM from being

    inferred.

Architecture Support
All architectures.
Applicable Objects

You can place this attribute on any signal, register, or wire.

  • get_nets
  • get_cells
Values
  • TRUE: Keeps the signal.
  • FALSE: Allows the Vivado synthesis to optimize, if the tool makes that determination. The FALSE value does not force the tool to remove the signal. The default value is FALSE.

Syntax

The syntax examples in this section show how to use this constraint with particular tools or methods. If a tool or method is not listed, you cannot use this constraint with it.

Verilog Syntax

Place the Verilog constraint immediately before the module or instantiation. Specify the Verilog constraint as follows:

(* KEEP = “{TRUE|FALSE|SOFT}” *)

Verilog Example:

(* keep = “true” *) wire sig1; 
assign sig1 = in1 & in2; 
assign out1 = sig1 & in2;
VHDL Syntax

Declare the VHDL constraint as follows:

attribute keep : string;

Specify the VHDL constraint as follows:

attribute keep of signal_name : signal is “{TRUE|FALSE}”;

VHDL Example:

signal sig1 : std_logic; 
attribute keep : string;
attribute keep of sig1 : signal is “true”;
....
....
sig1 <= in1 and in2; 
out1 <= sig1 and in3;
XDC Syntax

Not applicable

Affected Steps

  • Synthesis