IO_BUFFER_TYPE - 2024.1 English

Vivado Design Suite Properties Reference Guide (UG912)

Document ID
UG912
Release Date
2024-06-05
Version
2024.1 English

Apply IO_BUFFER_TYPE on a top level port to tell the tool to use IBUFs and OBUFs, or not to use input or output buffers. This attribute can be placed on any primary port or signal.

By default, Vivado synthesis infers input buffers for input ports, and infers output buffers for output ports. However, you can manually use the IO_BUFFER_TYPE property to disable this default behavior for specific ports or nets.

Note: The use of the IO_BUFFER_TYPE property implies a KEEP on the target net, which preserves the net name and prevents removing the net through RTL optimization.

The IO_BUFFER_TYPE can be used with the CLOCK_BUFFER_TYPE property to determine the combination of buffers to be inferred for clock signals.

Applicable Objects
  • Ports Apply IO_BUFFER_TYPE to any top-level port to disable buffer insertion.
  • Nets Apply IO_BUFFER_TYPE to any signal connected to a top-level port to disable buffer insertion.
Note: The property IO_BUFFER_TYPE is only available from HDL for Synthesis.
Values
NONE: Specify this value on input or output ports. The presence of this property indicates that no input or output buffers are to be inferred

Syntax

Verilog Syntax
(* io_buffer_type = "none" *) input in1;
VHDL Syntax
entity test is port(
in1 : std_logic_vector (8 downto 0); 
clk : std_logic;
out1 : std_logic_vector(8 downto 0)); 
attribute io_buffer_type : string;
attribute io_buffer_type of out1: signal is "none"; 
end test;
XDC Syntax

Not applicable.

Affected Steps

  • Synthesis