POST_CRC_SOURCE - 2024.1 English

Vivado Design Suite Properties Reference Guide (UG912)

Document ID
UG912
Release Date
2024-05-30
Version
2024.1 English

The Post CRC Source (POST_CRC_SOURCE) constraint specifies the source of the CRC value when the configuration logic CRC error detection feature is used for notification of any possible change to the configuration memory. This feature is only supported in 7 series FPGAs. For more information refer to the 7 Series FPGAs Configuration User Guide (UG470).

Tip: Alternatively, AMD recommends use of the AMD Soft Error Mitigation (SEM) IP for all architectures. This IP automates the implementation of single event upset (SEU) detection and correction. For additional information, refer to the Soft Error Mitigation Controller LogiCORE IP Product Guide (PG036).

This property is only applicable when POST_CRC is set to ENABLE. Enabling the POST_CRC property controls the generation of a pre-computed CRC value in the bitstream. As the configuration data frames are loaded, the device calculates a Cyclic Redundancy Check (CRC) value from the configuration data packets.

The POST_CRC_SOURCE property defines the expected CRC value as either coming from a pre-computed value, or as being taken from the configuration data in the first readback pass.

Architecture Support
7 series FPGAs.
Applicable Objects
Design (current_design): The current implemented design.
Values
  • PRE_COMPUTED: Determine an expected CRC value from the bitstream (default).
  • FIRST_READBACK: Extract the actual CRC value from the first readback pass, to use for comparison with future readback iterations.

Architecture Support

7 series FPGAs.

Syntax

Verilog Syntax

Not applicable

VHDL Syntax

Not applicable

XDC Syntax
set_property POST_CRC_SOURCE FIRST_READBACK | PRE_COMPUTED [current_design]

XDC Syntax Example

set_property POST_CRC_SOURCE PRE_COMPUTED [current_design]

Affected Steps

  • Write Bitstream
  • launch_runs