Introduction - 2024.1 English

Vivado Design Suite Properties Reference Guide (UG912)

Document ID
UG912
Release Date
2024-05-30
Version
2024.1 English

This reference manual discusses the first class objects, and the properties available for those objects, in the AMD Vivado™ Design Suite. It consists of the following:

Vivado Design Suite First Class Objects
Describes the various design and device objects used by the Vivado Design Suite to model the FPGA design database. Presents the objects sorted according to specific categories, with links to detailed object descriptions in the next chapter.
Alphabetical List of First Class Objects
List the Vivado Design Suite first class objects in alphabetical order. A definition of the object, a list of related objects, and a list of properties attached to each object are provided.
Key Property Descriptions
For many Vivado Design Suite properties, a description, supported architectures, applicable elements, values, syntax examples (Verilog, VHDL, and Xilinx Design Constraints (XDC)), and affected steps in the design flow are provided.
Additional Resources and Legal Notices
Resources and documents available on the AMD support website at www.xilinx.com/support are provided.