A register stage can be pulled out through SLR input or pushed into SRL input using the SRL_STAGES_TO_REG_INPUT property.
This provides control on pipeline register structures to address under and over-pipeline at the input side of SRL primitives.
- Architecture Support
- All architectures.
- Applicable Objects
- Cells (
get_cells) as leaf level SRL instances. - Values
-
- 1: The Vivado logic optimization will pull out a register from the specified SRL primitive(s) input.
- -1: The Vivado logic optimization will push a register into a specified SRL primitive(s) input.
Syntax
- Verilog Syntax
-
Not applicable
- VHDL Syntax
-
Not applicable
- XDC Syntax
-
set_property SRL_STAGES_TO_REG_INPUT <1 | -1> <objects>The objects should be SRLs, and the registers to be absorbed into the SRL should share the same control set with no reset.
XDC Example:
set_property SRL_STAGES_TO_REG_INPUT 1 [get_cells {cell1 cell2}]
Affected Steps
- Opt Design