SRL_STAGES_TO_REG_OUTPUT - 2024.1 English

Vivado Design Suite Properties Reference Guide (UG912)

Document ID
UG912
Release Date
2024-05-30
Version
2024.1 English

A register stage can be pulled out from SLR output or pushed into SRL output using the SRL_STAGES_TO_REG_OUTPUT property.

This provides control on pipeline register structures to address under and over-pipeline at the output side of SRL primitives.

Architecture Support
All architectures.
Applicable Objects
Cells (get_cells) as leaf level SRL instances.
Values
  • 1: The Vivado logic optimization will pull out a register from the specified SRL primitive(s) output.
  • -1: The Vivado logic optimization will push a register into a specified SRL primitive(s) output.

Syntax

Verilog Syntax

Not applicable

VHDL Syntax

Not applicable

XDC Syntax
set_property SRL_STAGES_TO_REG_OUTPUT <1 | -1> <objects>

The objects should be SRLs, and the registers to be absorbed into the same SRL should share the same control set with no reset.

XDC Example:

set_property SRL_STAGES_TO_REG_OUTPUT 1 [get_cells {cell1 cell2}]

Affected Steps

  • Opt Design