BLI - 2024.1 English

Vivado Design Suite Properties Reference Guide (UG912)

Document ID
UG912
Release Date
2024-05-30
Version
2024.1 English

The Boundary Logic Interface (BLI) constraint instructs the Vivado placer to place a flip flop cell into the BLI resources that exist at the interface between Programmable Logic and XPIO/AI Engine resources. BLI resources can help optimize the timing of the interface. The Vivado placer will only place the flip-flop cell into the BLI resource if connectivity, control set, and initial value criteria are met.

Architecture Support

Versal Adaptive SoCs

Applicable Objects

Flip-flop cells (get_cells) connected to applicable XPIO or AI Engine primitives.

Value

TRUE
The flip-flop cell will be placed into the BLI resource if connectivity, control set, and initial value criteria are met.
FALSE
The flip-flop cell will not be placed into the BLI resource (default).
AUTO
Currently unsupported.

Syntax

VHDL Syntax

Not applicable

Verilog Syntax

Not applicable

XDC Syntax
set_property BLI <TRUE | FALSE> [get_cells <ff_cells>]

XDC Syntax Examples:

# Use BLI Flip flop
set_property BLI TRUE [get_cells myHier/myBliFlop]

Affected Steps

  • Implementation

See Also

  • Versal Adaptive SoC AI Engine Architecture Manual (AM009)
  • Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010)