The Boundary Logic Interface (BLI) constraint instructs the Vivado placer to place a flip flop cell into the BLI resources that exist at the interface between Programmable Logic and XPIO/AI Engine resources. BLI resources can help optimize the timing of the interface. The Vivado placer will only place the flip-flop cell into the BLI resource if connectivity, control set, and initial value criteria are met.
Architecture Support
Versal adaptive SoCs
Applicable Objects
Flip-flop cells (get_cells) connected to applicable XPIO or AI Engine primitives.
Value
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TRUE - The flip-flop cell will be placed into the BLI resource if connectivity, control set, and initial value criteria are met.
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FALSE - The flip-flop cell will not be placed into the BLI resource (default).
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AUTO - Currently unsupported.
Syntax
- VHDL Syntax
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Not applicable
- Verilog Syntax
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Not applicable
- XDC Syntax
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set_property BLI <TRUE | FALSE> [get_cells <ff_cells>]XDC Syntax Examples:
# Use BLI Flip flop set_property BLI TRUE [get_cells myHier/myBliFlop]
Affected Steps
- Implementation