CLOCK_DEDICATED_ROUTE - 2024.1 English

Vivado Design Suite Properties Reference Guide (UG912)

Document ID
UG912
Release Date
2024-05-30
Version
2024.1 English

The CLOCK_DEDICATED_ROUTE property is enabled (TRUE) by default, and ensures that clock resource placement DRCs are considered error conditions that must be corrected prior to routing or bitstream generation. CLOCK_DEDICATED_ROUTE=FALSE downgrades the placement DRC to a warning and lets the Vivado router use fabric routing to connect from a clock-capable IO (CCIO) to a global clock resource such as an MMCM.

CAUTION:
Setting CLOCK_DEDICATED_ROUTE to FALSE can result in sub-optimal clock delays, resulting in potential timing violations and other issues.

External user clocks must be brought into the FPGA on differential clock pin pairs called clock-capable inputs (CCIO). These CCIOs provide dedicated, high-speed routing to the internal global and regional clock resources to guarantee timing of various clocking features. Refer to the 7 Series FPGAs Clocking Resources User Guide (UG472), or the UltraScale Architecture Clocking Resources User Guide (UG572) for more information on clock placement rules.

The CLOCK_DEDICATED_ROUTE property is generally used when it becomes necessary to place clock components in such a way as to take clock routing off of the dedicated clock trees in the target FPGA, and use standard routing channels. If the dedicated routes are not available, setting CLOCK_DEDICATED_ROUTE to FALSE demotes a clock placement DRC from an ERROR to a WARNING when a clock source is placed in a sub-optimal location compared to its load clock buffer.

Architecture Support

All architectures.

Applicable Objects

Nets (get_nets) directly connected to the input of a global clock buffer (BUFG, BUFGCE, BUFGMUX, BUGCTRL).

Important: CLOCK_DEDICATED_ROUTE must be set on a net segment at the highest level of design hierarchy, or the top-level net.

Value

7 series devices
TRUE
Default clock placement and routing.
BACKBONE
Clock driver and load(s) must be placed in the same Clock Management Tile (CMT) column. The clock routing still uses dedicated global clock routing resources.
FALSE
Clock driver and load(s) can be placed anywhere in the device. The clock net can be routed with both global clock routing resources, and standard fabric routing resources. This can adversely affect the timing and performance of the clock net.
UltraScale and Versal architectures
TRUE
Default clock placement and routing.
SAME_CMT_COLUMN (BACKBONE can also be used)
Clock driver and load(s) must be placed in the same Clock Management Tile (CMT) column. The clock routing uses dedicated global clock routing resources.
SAME_CMT_ROW (Versal devices only)
Clock driver and load(s) must be placed in the same Clock Management Tile (CMT) row, also called Horizontal Special Region (HSR). The clock routing uses dedicated global clock routing resources.
ANY_CMT_COLUMN
Clock driver and load(s) can be placed in any CMT column and the net uses dedicated global clock routing resources.
Note: This option is not available in 7 series devices.
FALSE
Clock driver and load(s) can be placed anywhere in the device. The clock net can be routed with both global clock routing resources, and standard fabric routing resources. This can adversely affect the timing and performance of the clock net.

Syntax

Verilog Syntax

Not applicable

VHDL Syntax

Not applicable

XDC Syntax
set_property CLOCK_DEDICATED_ROUTE [TRUE | FALSE | BACKBONE] [get_nets net_name]

Where net_name is the signal name directly connected to the input of a global clock buffer.

XDC Syntax Example:

# Designates clk_net to have relaxed clock placement rules 
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_net]

Affected Steps

  • Place Design
  • report_drc