MAX_FANOUT - 2024.1 English

Vivado Design Suite Properties Reference Guide (UG912)

Document ID
UG912
Release Date
2024-06-05
Version
2024.1 English

MAX_FANOUT constrains Vivado synthesis and placer to limit fanout on registers and signals, replicating drivers as needed to stay within the MAX_FANOUT limit. The value is specified as an integer.

Important: Use MAX_FANOUT sparingly during synthesis. The place_design command in the Vivado tools perform placement-based replication, which is more effective than logical replication in synthesis. If a specific fanout is desired, it is often worth the time and effort to manually code the extra registers.

This attribute only works on registers and combinatorial signals. To meet the specified fanout limit, Vivado synthesis replicates the register or the driver that drives the combinatorial signal. This attribute can be set in the RTL or the XDC.

MAX_FANOUT is also used during placement optimization when the placer can replicate registers driving high-fanout nets, or registers driving nets with loads that are placed far apart, or nets with a MAX_FANOUT property value that has not been satisfied. Fanout optimization occurs early in the placement flow, reducing the timing critical aspect of paths before starting detailed placement.

When the MAX_FANOUT value is less than the actual fanout of the constrained net the net is always evaluated for replication, but the optimization can be skipped if timing does not improve. The post-replication fanout will not necessarily match the MAX_FANOUT constraint value.

Architecture Support
All devices.
Applicable Objects
Registers and combinatorial signals in RTL and net objects in synthesized designs.
Values
<Integer>:The MAX_FANOUT value is a fanout limit that guides synthesis and placer to replicate MAX_FANOUT drivers until the fanout is at or below the fanout limit. For synthesis the MAX_FANOUT value refers to the logical fanout, the fanout in the logical netlist. For placement the value refers to the physical fanout, the site-based fanout after placement.

Syntax

Verilog Syntax

On Signal:

(* max_fanout = 50 *) reg sig1;
VHDL Syntax
signal sig1 : std_logic; 
attribute max_fanout : integer;
attribute max_fanout of sig1: signal is 50;
XDC Syntax
set_property MAX_FANOUT <number> [get_nets -hier <net_name>]

Affected Steps

  • Synthesis
  • Place Design