USER_SLR_ASSIGNMENT - 2024.1 English

Vivado Design Suite Properties Reference Guide (UG912)

Document ID
UG912
Release Date
2024-05-30
Version
2024.1 English

When placing design elements on stacked silicon interconnect (SSI) devices, you can use USER_SLR_ASSIGNMENT, USER_CROSSING_SLR, and USER_SLL_REG properties to manage logic partitioning, and the behavior of the Vivado placement tool. SSI devices consist of multiple super logic regions (SLRs), joined by interposer connections called super long lines (SLLs). For more information on placing and routing in and across SLRs, refer to this link in the UltraFast Design Methodology Guide for FPGAs and SoCs (UG949).

The USER_SLR_ASSIGNMENT property lets you specify the placement of cells into a defined super logic region (SLR), or grouped together into the same SLR without defining a specific SLR. The property has two forms, as defined in the Value section below: SLRn which defines a specific SLR to place the cells into, or group_name which groups cells together to be placed into the same SLR, though not a specific SLR.

Important: This property is considered a guideline which the placer will attempt to follow, but can be overridden to achieve a valid placement result.

To manage placement across SLRs, start with USER_SLR_ASSIGNMENT to assign logic to an SLR or group, add USER_CROSSING_SLR to control which net segment in the logic crosses the SLR boundary, and add USER_SLL_REG if necessary. USER_SLR_ASSIGNMENT has the highest priority. Use that together with USER_CROSSING_SLR to control individual nets/pins crossing the SLR boundary.

Architecture Support
All architectures.
Applicable Objects
Cells (get_cells) as hierarchical modules.
Value
  • SLRn: Where ā€˜nā€™ is an integer representing a specific SLR in a device. The placer will attempt to keep the contents of the hierarchical cell within the specified SLR.
  • group_name: This is a unique string value that can be assigned to one or more hierarchical cells or modules. The placer will try to place the cells or module with a common group_name into a single SLR, but the specific SLR is not important.

Syntax

Verilog Syntax

Not applicable

VHDL Syntax

Not applicable

XDC Syntax
set_property USER_SLR_ASSIGNMENT <SLRn | group_name> <objects>

XDC Example 1:

set_property USER_SLR_ASSIGNMENT SLR1 [get_cells {cell1 cell2}]

The placer will try to avoid partitioning cells cell1 and cell2 and try to place them in SLR1.

XDC Example 2:

set_property USER_SLR_ASSIGNMENT group_1 [get_cells {cell1 cell2}]

The placer will try to avoid partitioning cell1 and cell2 and try to place them in the same SLR, but the specific SLR is not important.

Affected Steps

  • Place Design