PULLUP applies a weak logic High on a tri-stateable output or bidirectional port to prevent it from floating. The PULLUP property guarantees a logic High level to allow tri-stated nets to avoid floating when not being driven.
Input buffers (for example, IBUF), 3-state output buffers (for example, OBUFT), and bidirectional buffers (for example, IOBUF) can have a weak pull-up resistor, a weak pull-down resistor, or a weak “keeper” circuit. This feature can be invoked by adding the PULLTYPE property with one of the following values to the port object connected to the buffer:
- PULLUP
- PULLDOWN
- KEEPER
For more information see the Vivado Design Suite 7 Series FPGA and Zynq 7000 SoC Libraries Guide (UG953) or the UltraScale Architecture Libraries Guide (UG974).
- Architecture Support
- All architectures.
- Applicable Objects
- Ports (
get_ports): Apply to any top-level port. - Values
-
-
TRUE|YES: Use a pullup circuit to avoid signal floating when not being driven. -
FALSE|NO: Do not use a pullup circuit (default).
-
Syntax
- Verilog Syntax
-
Place the Verilog attribute immediately before the module or instantiation. Specify as follows:
(* PULLUP = " {YES|NO|TRUE|FALSE}" *) - VHDL Syntax
-
Declare the VHDL attribute as follows:
attribute pullup: string;Specify the VHDL attribute as follows:
attribute pullup of signal_name : signal is “{YES|NO|TRUE|FALSE}”; - XDC Syntax
-
set_property PULLUP {TRUE|FALSE} [get_ports port_name]Where
port_nameis the name of an input, output, or inout port.XDC Syntax Example
set_property PULLUP TRUE [get_ports wbWriteOut]
Affected Steps
- Logical to Physical Mapping