CASCADE_HEIGHT - 2024.1 English

Vivado Design Suite Properties Reference Guide (UG912)

Document ID
UG912
Release Date
2024-06-05
Version
2024.1 English

The CASCADE_HEIGHT attribute is an integer used to describe the length of the cascade chains of large RAMS that are put into block RAMs. When an inferred RAM is deeper than a single RAM block, the Vivado synthesis tool can map the array to a cascade of RAM blocks instead.

Often, the Vivado synthesis tool chooses to cascade the block RAMs that it creates. This attribute can be used to shorten or limit the length of the chain. A value of 0 or 1 for this attribute effectively turns off any cascading of block RAMs.

This attribute can be placed on the RAM array in the RTL source files, or in an XDC file, to drive synthesis.

Architecture Support

UltraScale , UltraScale+, and Versal architectures.

Applicable Objects

RAM Cells (get_cells)

Value

<VALUE>: Specify an integer.

Syntax

VHDL Syntax
attribute cascade_height : integer;
attribute cascade_height of ram : signal is 4;
Verilog Syntax
(* cascade_height = 4 *) reg [31:0] ram [(2**15) - 1:0];
XDC Syntax
set_property CASCADE_HEIGHT 4 [get_cells my_RAM_reg]

Affected Steps

  • Synthesis