USE_DSP - 2024.1 English

Vivado Design Suite Properties Reference Guide (UG912)

Document ID
UG912
Release Date
2024-05-30
Version
2024.1 English

The USE_DSP property directs the Vivado Design Suite to synthesize mathematical modules into DSP blocks on the targeted device.

Tip: TIP: USE_DSP48 is deprecated, and should be replaced by USE_DSP.

By default, multipliers (mults), mult-add, mult-sub, mult-accumulate type structures are assigned into DSP blocks. However, adders, subtractors, and accumulators can also go into DSP blocks, but by default are implemented with logic instead. The USE_DSP attribute overrides the default behavior and defines these structures using DSPs.

DSPs can also be used to implement many other logic functions, beyond mathematics, such as counters, multiplexers, and shift registers. However, for complex modules such as multiplexers, you need to manually instantiate DSPs.

This property can be placed in the RTL as an attribute on signals, for example:

(* use_dsp = "yes" *) module test(clk, in1, in2, out1);

You can apply USE_DSP to a module in the RTL source, but it only applies to the module it is specified on. You can also apply it to hierarchical cells in the design as an XDC constraint.

Architecture Support
All devices
Applicable Objects
This attribute can be placed in the RTL on signals, architectures and components, entities and modules. The priority is as follows:
  1. Signals
  2. Architectures and components
  3. Modules and entities
Values
  • YES: Use the DSP blocks to implement mathematical functions.
  • NO: Do not change the default behavior of Vivado synthesis.
  • LOGIC: For UltraScale architecture only. Use the DSP blocks to implement large/wide XOR functions.

Syntax

Verilog Syntax
(* use_dsp = "yes" *) module test(clk, in1, in2, out1);
VHDL Syntax
attribute use_dsp : string;
attribute use_dsp of P_reg : signal is "no"
XDC Syntax
set_property use_dsp yes [get_cells -hier ….]

Affected Steps

  • Synthesis