HW_SIO_PLL - 2024.1 English

Vivado Design Suite Properties Reference Guide (UG912)

Document ID
UG912
Release Date
2024-05-30
Version
2024.1 English

Description

For AMD FPGA devices having GigaBit Transceivers (GTs), each serial transceiver channel has a ring phase-locked loop (PLL) called Channel PLL (CPLL). For AMD UltraScale and 7 series FPGAs, the GTX has an additional shared PLL per quad, or Quad PLL (QPLL). This QPLL is a shared LC PLL to support high speed, high performance, and low power multi-lane applications.

Related Objects

HW_SIO_PLL objects are associated with hw_server, hw_target, hw_device, hw_sio_ibert, hw_sio_gt, or hw_sio_common objects.

You can query the PLLs of associated objects:

get_hw_sio_plls -of [get_hw_sio_commons]

And you can query the objects associated with a PLL:

get_hw_sio_iberts -of [get_hw_sio_plls *MGT_X0Y8/CPLL_0]

Properties

You can use the report_property command to report the properties assigned to a specific HW_SIO_PLL. Refer to the Vivado Design Suite Tcl Command Reference Guide (UG835) for more information. The properties assigned to a shared QPLL type of HW_SIO_PLL object includes the following, with example values:

Property	Type	Read-only	Visible	Value
CLASS	string	true	true	hw_sio_pll
DISPLAY_NAME	string	true	true	COMMON_X0Y2/QPLL_0
DRP.QPLL_CFG	string	false	true	06801C1
DRP.QPLL_CLKOUT_CFG	string	false	true	0
DRP.QPLL_COARSE_FREQ_OVRD	string	false	true	10
DRP.QPLL_COARSE_FREQ_OVRD_EN	string	false	true	0
DRP.QPLL_CP	string	false	true	01F
DRP.QPLL_CP_MONITOR_EN	string	false	true	0
DRP.QPLL_DMONITOR_SEL	string	false	true	0
DRP.QPLL_FBDIV	string	false	true	0E0
DRP.QPLL_FBDIV_MONITOR_EN	string	false	true	1
DRP.QPLL_FBDIV_RATIO	string	false	true	1
DRP.QPLL_INIT_CFG	string	false	true	000028
DRP.QPLL_LOCK_CFG	string	false	true	21E8
DRP.QPLL_LOWER_BAND	string	false	true	1
DRP.QPLL_LPF	string	false	true	F
DRP.QPLL_REFCLK_DIV	string	false	true	10
LOGIC.QPLLRESET_CTRL	string	false	true	0
LOGIC.QPLLRESET_STAT	string	false	true	0
LOGIC.QPLL_LOCK	string	false	true	0
NAME	string	true	true	
localhost/xilinx_tcf/Digilent/210203327463A/0_1/IBERT/Quad_117/COMMON_X0Y2/QPLL_0 PARENT	string	true	true localhost/xilinx_tcf/Digilent/210203327463A/0_1/IBERT/Quad_117/COMMON_X0Y2
PORT.QPLLDMONITOR	string	false	true	EC
PORT.QPLLFBCLKLOST	string	false	true	0
PORT.QPLLLOCK	string	false	true	1
PORT.QPLLLOCKEN	string	false	true	1
PORT.QPLLOUTRESET	string	false	true	0
PORT.QPLLPD	string	false	true	0
PORT.QPLLREFCLKLOST	string	false	true	0
PORT.QPLLREFCLKSEL	string	false	true	1
PORT.QPLLRESET	string	false	true	0
PORT.QPLLRSVD1	string	false	true	0000
PORT.QPLLRSVD2	string	false	true	1F
QPLLREFCLKSEL	enum	false	true	GTREFCLK0
QPLL_N_DIVIDER	enum	false	true	64
QPLL_REFCLK_DIV	enum	false	true	1
STATUS	string	false	true	LOCKED

To report the properties of the HW_SIO_PLL object, you can copy and paste the following command into the Vivado Design Suite Tcl shell or Tcl Console:

report_property -all [lindex [get_hw_sio_plls] 0]