An SRL primitive can be converted to a logically equivalent chain of register primitives using the SRL_TO_REG property with a value of true. This transform is typically used to increase the number of available pipeline register stages that can be spread to allow signals to traverse long distances within a device.
- Architecture Support
- All architectures.
- Applicable Objects
- Cells (
get_cells) as leaf level SRL instances. - Values
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- 1: The Vivado logic optimization will pull out a register from the specified SRL primitive(s) input.
Syntax
- Verilog Syntax
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Not applicable
- VHDL Syntax
-
Not applicable
- XDC Syntax
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set_property SRL_TO_REG <True | False> <objects>The property is false by default. The objects should be static shift registers which can be instantiated or inferred, e.g., SRL16E, SRL32E.
XDC Example:
set_property SRL_TO_REG 1 [get_cells {cell1 cell2}]
Affected Steps
- Opt Design