PULLTYPE - 2024.1 English

Vivado Design Suite Properties Reference Guide (UG912)

Document ID
Release Date
2024.1 English
Important: The PULLTYPE property replaces KEEPER, PULLDOWN, and PULLUP properties, which have been deprecated.

Input buffers (for example, IBUF), 3-state output buffers (for example, OBUFT), and bidirectional buffers (for example, IOBUF) can have a weak pull-up resistor, a weak pull-down resistor, or a weak “keeper” circuit. This feature can be invoked by adding the PULLTYPE property with one of the following properties to the port or net object connected to the buffer:

Note: When this property is applied, the KEEPER, PULLDOWN, or PULLUP functionality will not be shown during RTL simulation which can create a functional difference between the RTL simulation results and the implemented design. This functionality can be verified by using the post-synthesis gate-level netlist which includes the object; or by instantiating the appropriate UNISIM object into the design in place of using the PULLTYPE property to reflect this behavior in the RTL simulation.

For differential inputs or outputs, you can set the following parameter to define the preferred termination strategy:

set_param iconstr.diffPairPulltype { auto | same | opposite }


  • AUTO: This is the default for all architectures.
    • For 7 series devices, AUTO has the same effect as SAME.
    • For UltraScale and UltraScale+ architecture, AUTO has the same effect as OPPOSITE.
  • SAME: both the positive and negative side are PULLUP or PULLDOWN, as defined by the PULLTYPE property.
  • OPPOSITE: If the PULLTYPE of the P-side is assigned a PULLUP, then the N-side is assigned a PULLDOWN.

For more information see the Vivado Design Suite 7 Series FPGA and Zynq 7000 SoC Libraries Guide (UG953) or the UltraScale Architecture Libraries Guide (UG974).

Architecture Support
All architectures.
Applicable Objects
Ports (get_ports): Apply to any top-level port.
  • KEEPER: Use a keeper circuit to preserve the value on the net connected to the specified port.
  • PULLDOWN: Use a pulldown circuit to avoid signal floating when not being driven.
  • PULLUP: Use a pullup circuit to avoid signal floating when not being driven.
  • {}: (NULL) Do not use a keeper, pulldown, or pullup circuit (default).


Verilog Syntax

Place the Verilog attribute immediately before the module or instantiation. Specify as follows:

VHDL Syntax

Declare the VHDL attribute as follows:

attribute PULLTYPE: string;

Specify the VHDL attribute as follows:

attribute PULLTYPE of signal_name : signal is “{KEEPER|PULLDOWN|PULLUP| }”;
XDC Syntax
set_property PULLTYPE {KEEPER|PULLDOWN|PULLUP| } [get_ports port_name]

Where port_name is the name of an input, output, or inout port.

XDC Syntax Example:

set_property PULLTYPE PULLUP [get_ports wbWriteOut]


set_property PULLTYPE {} [get_ports wbWriteOut]

Affected Steps

  • Logical to Physical Mapping