PORT - 2024.1 English

Vivado Design Suite Properties Reference Guide (UG912)

Document ID
UG912
Release Date
2024-05-30
Version
2024.1 English

Description

A port is a special type of hierarchical pin, providing an external connection point at the top-level of a hierarchical design, or an internal connection point in a hierarchical cell or block module to connect the internal logic to the pins on the hierarchical cell. Ports can be scalar, containing a single connection, or can be bus ports to group multiple signals together.

Figure 1. PORT Objects

Related Objects

Ports at the top level of the design make connection outside the FPGA through the PACKAGE_PINs of the device package, to IO_BANKs on the die, with assigned IOSTANDARDs.

Ports can also carry clock definitions onto the design from the system or board, and should be assigned external system-level path delay using the set_input_delay or set_output_delay constraints. Refer to the Vivado Design Suite User Guide: Using Constraints (UG903) for more information on these constraints.

You can query the ports assigned to specific package_pins, IO_banks, IO_Standards, sites, cells, nets, clocks, timing_paths, or drc_violations using a Tcl command like the following:

get_ports -of [get_clocks]

Inside the design, ports are connected to cells, through nets, to build the hierarchical netlist. You can query the objects associated with a port, such as net, timing_path, site, io_bank, io_standard, package_pin, pkgpin_bytegroup, pkgpin_nibble, using the following form of command:

get_package_pins -of [all_inputs]

Properties

The properties found on ports objects are as follows, with example values:

Property	Type	Read-only	Visible	Value
BOARD_PART_PIN	string	false	true	
BOARD_PIN	string	false	false	
BUFFER_TYPE	enum	false	true	
BUS_DIRECTION	enum	true	true	
BUS_NAME	string	true	true	
BUS_START	int	true	true	
BUS_STOP	int	true	true	
BUS_WIDTH	int	true	true	
CLASS	string	true	true	port
CLOCK_BUFFER_TYPE	enum	false	true	
DIFFTERMTYPE	bool	false	false	0
DIFF_PAIR_PORT	string	true	true	
DIFF_PAIR_TYPE	enum	true	true	
DIFF_TERM	bool	false	true	0
DIRECTION	enum	false	true	IN
DQS_BIAS	enum	false	true	
DRIVE	enum	false	true	12
DRIVE_STRENGTH	enum	false	false	12
ESSENTIAL_CLASSIFICATION_VALUE	int	false	true	
HD.ASSIGNED_PPLOCS	string*	true	true	
HD.CLK_SRC	string	false	true	
HD.LOC_FIXED	bool	false	false	0
HD.PARTPIN_LOCS	string*	false	true	
HD.PARTPIN_RANGE	string*	false	true	
HD.PARTPIN_TIEOFF	bool	false	true
HOLD_SLACK	double	true	true	needs timing update***
IBUF_LOW_PWR	bool	false	true	0
INTERFACE	string	false	true
INTERMTYPE	enum	false	false	NONE
IN_TERM	enum	false	true	NONE
IOB	enum	false	true	
IOBANK	int	true	true	33
IOSTANDARD	enum	false	true	LVCMOS18
IOSTD	enum	false	false	LVCMOS18
IO_BUFFER_TYPE	enum	false	true	
IS_BEL_FIXED	bool	false	false	1
IS_FIXED	bool	false	false	1
IS_GT_TERM	bool	true	true	0
IS_LOC_FIXED	bool	false	true	1
IS_REUSED	bool	true	true	
KEEP	string	false	true	
KEEPER	bool	false	false	0
LOAD	double	false	true	
LOC	site	false	true	IOB_X1Y43
LOGIC_VALUE	string	true	true	unknown
NAME	string	false	true	reset
OFFCHIP_TERM	string	false	true	NONE
OUT_TERM	enum	false	true	
PACKAGE_PIN	package_pin	false	true	W9
PIN_TYPE	enum	true	false	
PIO_DIRECTION	enum	false	true	
PULLDOWN	bool	false	false	0
PULLTYPE	string	false	true	
PULLUP	bool	false	false	0
SETUP_SLACK	double	true	true	needs timing update***
SITE	site	false	false	IOB_X1Y43
SLEW	enum	false	true	
SLEWTYPE	enum	false	false	
SLEW_ADV	enum	false	false	
UNCONNECTED	bool	true	true	0
USE_INTERNAL_VREF	enum	false	true	
VCCAUX_IO	enum	false	true	
XLNX_LINE_COL	int	false	false	
XLNX_LINE_FILE	long	false	false	
X_INTERFACE_INFO	string	false	true	

The properties of ports can be listed with the following command:

report_property -all [lindex [get_ports] 0]