IOB_TRI_REG - 2024.1 English

Vivado Design Suite Properties Reference Guide (UG912)

Document ID
UG912
Release Date
2024-05-30
Version
2024.1 English

For UltraScale+ devices, the IOB_TRI_REG property tells the placer to place flip flops driving Tristate signals on High-density (HD) I/O banks in the I/O Logic (IOB) instead of the device fabric. Refer to the UltraScale Architecture SelectIO Resources User Guide (UG571) for more information on High Density I/O.

Tip: TIP: This property must be assigned to the register cell as an XDC constraint, it is not supported in HDL source files, and cannot be assigned to the port.
Architecture Support
UltraScale+ devices.
Applicable Objects
Cells (get_cells)
Values
  • TRUE: Place the specified tristate register into the HD I/O Block.
  • FALSE: Do not place the specified register into the I/O Block (default).

Syntax

Verilog Syntax

Not applicable

VHDL Syntax

Not applicable

XDC Syntax
set_property IOB_TRI_REG value [get_cells <cell_name>]

Affected Steps

  • Place Design