TIMING_PATH - 2024.1 English

Vivado Design Suite Properties Reference Guide (UG912)

Document ID
UG912
Release Date
2024-05-30
Version
2024.1 English

Description

Timing paths are defined by connections between elements of the design. In digital designs, timing paths are formed by a pair of sequential elements controlled by the same clock, or by two different clocks to launch and capture the signal.

In a typical timing path, the data is transferred between two sequential cells within one clock period. For example, the launch edge occurs at time 0 ns; and the capture edge occurs one CLOCK period later.

The most common timing paths are:

  • Paths from an input port to a internal sequential cell
  • Internal paths from one sequential cell to another sequential cell
  • Paths from an internal sequential cell to an output port
  • Paths from an input port to an output port

Each timing path is defined by unique startpoints, throughpoints, and endpoints. A path startpoint is a sequential cell clock pin or a data input port; and a path endpoint is a sequential cell data input pin or a data output port.

TIMING_PATH objects can be selected or specified with varying degrees of details. A single unique timing path is defined by a combination of startpoint, throughpoint, and endpoint. Multiple timing paths can be specified from a common startpoint, or a common endpoint.

Constraints can be applied to timing paths as determined by the definition of the timing path. The order of precedence for constraints applied to timing paths, from highest to lowest, is as follows:

  1. -from -through -to (a unique timing path)
  2. -from -to
  3. -from -through
  4. -from
  5. -through -to
  6. -to
  7. -through (any timing path passing through this point)

For more information on timing paths refer to Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906).

Related Objects

Figure 1. TIMING_PATH Objects

TIMING_PATH objects can be queried using the get_timing_paths command. This allows you to specify timing paths using related CLOCK, PIN, PORT, or CELL objects to identify startpoints, throughpoints, or endpoints on the paths of interest.

get_timing_paths -from fftEngine/control_reg_reg[1] -max_paths 10

In addition, you can query the CELL, NET, PIN, or PORT objects associated with specified timing paths:

get_nets -of_objects [get_timing_paths -max_paths 10]

Properties

The properties on a TIMING_PATH object include the following, with example values:

Property	Type	Read-only	Visible	Value
CLASS	string	true	true	timing_path
CLOCK_PESSIMISM	double	true	true	-0.661
CORNER	string	true	true	Slow
DATAPATH_DELAY	double	true	true	6.934
DELAY_TYPE	string	true	true	max
ENDPOINT_CLOCK	clock	true	true	cpuClk_3
ENDPOINT_CLOCK_DELAY	double	true	true	-2.149
ENDPOINT_CLOCK_EDGE	double	true	true	20.000
ENDPOINT_PIN	pin	true	true	
cpuEngine/or1200_immu_top/qmemimmu_cycstb_o_reg/D
EXCEPTION	string	true	true	
GROUP	string	true	true	cpuClk_3
INPUT_DELAY	double	true	true	
INTER_SLR_COMPENSATION	double	true	true	
LOGIC_LEVELS	int	true	true	16
NAME	string	true	true	{usbEngine0/u4/inta_reg/C -->
cpuEngine/or1200_immu_top/qmemimmu_cycstb_o_reg/D}
OUTPUT_DELAY	double	true	true	
REQUIREMENT	double	true	true	10.000
SKEW	double	true	true	-0.057
SLACK	double	true	true	2.865
STARTPOINT_CLOCK	clock	true	true	usbClk_2
STARTPOINT_CLOCK_DELAY	double	true	true	-2.754
STARTPOINT_CLOCK_EDGE	double	true	true	10.000
STARTPOINT_PIN	pin	true	true	usbEngine0/u4/inta_reg/C
UNCERTAINTY	double	true	true	0.202
USER_UNCERTAINTY	double	true	true	

The properties of TIMING_PATH objects can be reported with the following command:

report_property -all [lindex [get_timing_paths] 0]