Description
A pin is a point of logical connectivity on a primitive or hierarchical cell. A pin allows the contents of a cell to be abstracted away, and the logic simplified for ease-of-use. Pins can be scalar, containing a single connection, or can be defined as bus pins to group multiple signals together.
Related Objects
A pin is attached to a cell and can be connected to pins on other cells by a net. The pins of cells are also related to the bel_pins of the bel object, or site_pins of a SITE that the cell is mapped to. Pins are associated with clocks as part of the clock domain, and are part of timing_paths when defined as the start point, end point, or through point of the path.
Pins can also be associated with drc_violations to allow you to more quickly locate and resolve design issues.
Properties
The PIN object includes a collection of properties that define the type of pin for clock and control pins. You can use these attributes to filter the list of pins by type when writing Tcl scripts, or working with PIN objects. The properties are listed in the following table.
| Property Name | Clock Relationship | Description | Example |
|---|---|---|---|
| IS_CLEAR | Asynchronous | Forces block output(s) to a 0 state. | CLR pin in the FDCE |
| IS_CLOCK | Reference | The pin has a setup/hold or recovery/removal relationship with another pin, and acts as the reference pin in that relationship. | The C pin on an FDRE |
| IS_ENABLE | Synchronous | Control that allows or inhibits the data capture of a block. | The CE pin on an FDRE |
| IS_PRESET | Asynchronous | Forces block output(s) to a 1 state. | The PRE pin on an FDPE |
| IS_RESET | Synchronous | Changes block output(s) to a 0 state at next clock. | The R pin on an FDRE |
| IS_SET | Synchronous | Changes block output(s) to a 1 state at next clock. | The S pin on an FDSE |
| IS_SETRESET | Programmable | Programmable synchronous or asynchronous set/reset. The pin's behavior is controlled by an attribute on the block. | The RSTRAMB pin on a RAMB36E2 |
| IS_WRITE_ENABLE | Synchronous | Enable pin that allows or inhibits the write operation on a memory block. | The WES pin on a RAMB36E2 |
Beyond these properties that define the pin type, the various properties found on PIN objects include the following:
Property Type Read-only Visible Value
BEL string false true
BUS_DIRECTION enum true true
BUS_NAME string true true
BUS_START int true true
BUS_STOP int true true
BUS_WIDTH int true true
CLASS string true true pin
CLOCK_DEDICATED_ROUTE enum false true
DCI_VALUE int false true
DIRECTION enum true true IN
ESSENTIAL_CLASSIFICATION_VALUE int false true
FB_ACTIVE bool false true
HD.ASSIGNED_PPLOCS string* true true
HD.CLK_SRC string false true
HD.LOC_FIXED bool false false 0
HD.PARTPIN_LOCS string* false true
HD.PARTPIN_RANGE string* false true
HD.PARTPIN_TIEOFF bool false true
HD.TANDEM int false true
HIERARCHICALNAME string true false
top.cpuEngine.dwb_biu.\retry_cntr_reg[0] .C
HOLD_DETOUR int false true
HOLD_SLACK double true true needs timing update***
IS_CLEAR bool true true 0
IS_CLOCK bool true true 1
IS_CONNECTED bool true true 1
IS_ENABLE bool true true 0
IS_INVERTED bool false true 0
IS_LEAF bool true true 1
IS_ORIG_PIN bool true true 0
IS_PRESET bool true true 0
IS_RESET bool true true 0
IS_REUSED bool true true 0
IS_SET bool true true 0
IS_SETRESET bool true true 0
IS_WRITE_ENABLE bool true true 0
LOGIC_VALUE string true true unknown
MARK_DEBUG bool false true
NAME string true true
cpuEngine/dwb_biu/retry_cntr_reg[0]/C
ORIG_PIN_NAME string true true
PARENT_CELL cell true true
cpuEngine/dwb_biu/retry_cntr_reg[0]
REF_NAME string true true FDCE
REF_PIN_NAME string true true C
SETUP_SLACK double true true needs timing update***
TARGET_SITE_PINS string* false true
XLNX_LINE_COL int false false
XLNX_LINE_FILE long false false
The properties of pins can be listed with the following command:
report_property -all [lindex [get_pins] 0]