BD_CELL - 2024.1 English

Vivado Design Suite Properties Reference Guide (UG912)

Document ID
UG912
Release Date
2024-06-05
Version
2024.1 English

Description

A block design cell, or bd_cell object, is an instance of an IP integrator IP core object, or is a hierarchical block design cell. A leaf-cell is a core from the IP catalog. A hierarchical cell is a module or block that contains one or more additional levels of logic, including leaf-cells.

The TYPE property of the bd_cell object identifies the block design cell as either a lead-cell coming from the IP catalog (TYPE == IP), or as a hierarchical module containing additional logic (TYPE == HIER).

Related Objects

Figure 1. Block Design Cells

As seen in figure above, Block design cells (bd_cell) are found in a block design, or diagram object. The cells include block design pins (bd_pin) and interface pins (bd_intf_pin), and can hierarchically contain block design ports (bd_port) and interface ports (bd_intf_port). They are connected by nets (bd_net) and interface nets (bd_intf_net). Memory related block design cells can also contain address spaces (bd_addr_space), and address segments (bd_addr_seg). You can query the block design cells that are associated with any of these objects, for example:

get_bd_cells -of_objects [get_bd_addr_spaces]

You can query the objects associated with block design cells:

get_bd_addr_spaces -of_objects [get_bd_cells]

You can also query the block design cells that are hierarchically objects of another block design cell:

get_bd_cells -of_objects [get_bd_cells microblaze_0_axi_periph]

Properties

The specific properties on a block design cell object can be numerous and varied, depending on the type of IP core the object represents. The following table lists some of the properties assigned to a bd_cell object in the Vivado Design Suite, with example values:

Property					Type		Read-only	Visible	Value
CLASS						string	 true		 true	bd_cell 
CONFIG.C_ALL_INPUTS	   string	 false		true	0
CONFIG.C_ALL_INPUTS_2	 string	 false		true	0
CONFIG.C_ALL_OUTPUTS	  string	 false		true	1
CONFIG.C_ALL_OUTPUTS_2	string	 false		true	0
CONFIG.C_DOUT_DEFAULT 	string 	false 	true 0x00000000 
CONFIG.C_DOUT_DEFAULT_2   string 	false 	true 0x00000000 
CONFIG.C_GPIO2_WIDTH 	 string 	false 	true 32
CONFIG.C_GPIO_WIDTH		string  	false      true    4
CONFIG.C_INTERRUPT_PRESENT    string  false      true    0
CONFIG.C_IS_DUAL			string  	false      true    0
CONFIG.C_TRI_DEFAULT	   string	 false	true	0xFFFFFFFF 
CONFIG.C_TRI_DEFAULT_2	 string	 false	true	0xFFFFFFFF 
CONFIG.Component_Name	  string	 false	true	base_mb_axi_gpio_0_0 
CONFIG.GPIO2_BOARD_INTERFACE	string	false	true	Custom 
CONFIG.GPIO_BOARD_INTERFACE	string	false	true	led_4bits 
CONFIG.USE_BOARD_FLOW	   string	false	true	true
LOCATION	string	false	true	5 1720 200
LOCK_UPGRADE	bool false true 0
NAME	string	false	true	axi_gpio_0
PATH	string	true	true	/axi_gpio_0
SCREENSIZE	string	false	true	180 116
SDX_KERNEL	string	true	false	false
SDX_KERNEL_SIM_INST	string	true	false 
SDX_KERNEL_SYNTH_INST	string	true	false 
SDX_KERNEL_TYPE	string	true	false 
SELECTED_SIM_MODEL	string	false	true	rtl 
TYPE	string	true	true	ip
VLNV	string	true	true	xilinx.com:ip:axi_gpio:2.0

To report the properties for a bd_cell object, you can copy and paste the following command into the Vivado Design Suite Tcl shell or Tcl Console:

report_property -all [lindex [get_bd_cells] 0]