USER_SLL_REG - 2024.1 English

Vivado Design Suite Properties Reference Guide (UG912)

Document ID
UG912
Release Date
2024-05-30
Version
2024.1 English

Stacked silicon interconnect (SSI) devices consist of multiple super logic regions (SLRs), joined by interposer connections called super long lines (SLLs). Paths crossing between SLRs through SLLs can present timing closure challenges.

USER_SLL_REG instructs the implementation tools to place the register in a location that is optimal for connections to the SLL. For UltraScale based architectures, this is a LAGUNA register. This is a dedicated register that drives data to, or receives data from the SLL. For Versal Adaptive SoCs based architectures, this selects a slice register that is adjacent to the SLL. The cells where the USER_SLL_REG property is set to true must be register cells, and should have FD/Q -> FD/D connectivity. The property can be set on either source or destination registers, or both the source and destination cells.

The property is ignored when:

  • none of the nets connected to FD/D or FD/Q cross an SLR boundary,
  • both nets connected to FD/D or FD/Q cross an SLR boundary,
  • FD/Q net crosses an SLR boundary and has loads in two different SLRs.

For an FD cell with the USER_SLL_REG property set to false, the placer will never place the cell on a nearby LAGUNA site (hard constraint).

To further refine the placement of the registers, you can use Pblocks. In UltraScale architectures, they should include the LAGUNA sites that you can achieve using a Pblock range that includes the clock region closest to the SLR boundary. For Versal Adaptive SoCs, they should be within 75 slices from the SLR boundary.

Important: This property is considered a guideline which the placer will attempt to follow, but can be overridden to achieve a valid placement result.
Architecture Support
All Architectures
Applicable Objects
Register Cells
Value
  • True (or 1): The Vivado placer will place (during detail placement) the FD cell at an optimal site, if the net connected to FD/D or FD/Q crosses an SLR boundary.
  • False (or 0): Do not place the register into a LAGUNA site. This is ignored for Versal devices.

Syntax

Verilog Syntax

Not applicable

VHDL Syntax

Not applicable

XDC Syntax
set_property USER_SLL_REG <True | False> <objects>

XDC Example:

set_property USER_SLL_REG 1 [get_cells {cell1 cell2}]

The placer will try to place cell1 and cell2 into Laguna registers at the SLR boundary.

Affected Steps

  • Place Design