The CLOCK_REGION property lets you assign a clock buffer to a specific clock region of an UltraScale device, while letting the Vivado placer assign the clock buffer to the best site within that region.
Important: For UltraScale devices,
it is not recommended to fix a Clock Buffer to a specific site, as you might do in
clock planning a 7 series design.
Instead, you can assign a Clock Buffer to a specific CLOCK_REGION and leave the
clock resources available to the Vivado placer to determine the
best clocking structure.
- Architecture Support
-
UltraScale and UltraScale+ architectures.
- Applicable Objects
-
- Global clock buffer cells (
get_cells)- BUFG cells (BUFGCE, BUFGCTRL, BUFG_GT, BUFGCE_DIV)
- Global clock buffer cells (
- Values
-
<VALUE>: Specify the CLOCK_REGION to place the cell or cells into. The CLOCK_REGION is specified by name as X#Y#, or as returned by theget_clock_regionsTcl command.Note: Refer to Vivado Design Suite Tcl Command Reference Guide (UG835) for more information on theget_clock_regionscommand.
Syntax
- Verilog Syntax
-
Not applicable
- VHDL Syntax
-
Not applicable
- XDC Syntax
-
set_property CLOCK_REGION X0Y2 [get_cells <cell>]Where
<cell>is an instance of a global clock buffer.XDC Syntax Example:
User assignment of the CLOCK_RERGION would be performed in XDC as follows:
set_property CLOCK_REGION X4Y6 [get_cells {sys_clk_pll/inst/clkf_buf}]
Affected Steps
- Place Design
- report_drc