H_SET and HU_SET - 2024.2 English - UG912

Hierarchical sets are collections of logic elements based on the hierarchy of the design as defined by the HDL source files. H_SET, HU_SET, and U_SET are attributes within the HDL design source files, and do not appear in the synthesized or implemented design. They are used when defining Relatively Placed Macros, or RPMs in the RTL design. For more information on using these properties, and defining RPMs, refer to the Vivado Design Suite User Guide: Using Constraints (UG903).

H_SET is a property that is implied due to the presence of RLOC properties on logic cells in the hierarchy of a design. Logic elements inside of a hierarchical block, that have the RLOC property, are automatically assigned to the same Hierarchical Set, or H_SET.

Each hierarchical module is assigned an H_SET property based on the instance name of the module. Each hierarchical module can only have a single H_SET name, and all logic elements inside that hierarchy are elements of that H_SET.

You can also manually create a User-defined Hierarchical Set, or HU_SET, or a User-defined Set, or U_SET, that is not dependent on the hierarchy of the design.

You can define multiple HU_SET names for a single hierarchical module, and assign specific instances of that hierarchy to the HU_SET. This allows you to divide the logic elements of a single hierarchical module into multiple HU_SETs.

When RLOC is also present in the RTL source files, the H_SET, HU_SET, and U_SET properties get translated to a read-only RPM property on cells in the synthesized netlist. The HU_SET and U_SET are visible on the RTL source file in the Text editor in the Vivado Design Suite. However, in the Properties window of a cell object, the RPM property is displayed.

Architecture Support

All architectures.

Applicable Objects

The HU_SET property can be used in one or more of the following design elements, or categories of design elements. Refer to the Vivado Design Suite 7 Series FPGA and Zynq 7000 SoC Libraries Guide (UG953) or the UltraScale Architecture Libraries Guide (UG974) for more information on the specific design elements:

• Registers
• LUT
• Macro Instance
• RAMS
• RAMD
• RAMB18/FIFO18
• RAMB36/FIFO36
• DSP48

Values

<NAME>: A unique name for the HU_SET

Syntax

Verilog Syntax

This is a Verilog attribute used in combination with the RLOC property to define the set content of a hierarchical block that will define an RPM in the synthesized netlist. Place the Verilog attribute immediately before the instantiation of a logic element.

(* RLOC = "X0Y0", HU_SET = "h0" *) FD sr0 (.C(clk), .D(sr_1n), .Q(sr_0));

Verilog Example:

The following Verilog module defines RLOC and HU_SET properties for the shift register Flops in the module.

module ffs ( 
input clk, 
input d, 
output q
);

wire sr_0, sr_0n; 
wire sr_1, sr_1n; 
wire sr_2, sr_2n; 
wire sr_3, sr_3n;
wire sr_4, sr_4n; 
wire sr_5, sr_5n; 
wire sr_6, sr_6n; 
wire sr_7, sr_7n;

wire	inr, inrn, outr;

inv i0 (sr_0, sr_0n); 
inv i1 (sr_1, sr_1n); 
inv i2 (sr_2, sr_2n); 
inv i3 (sr_3, sr_3n); 
inv i4 (sr_4, sr_4n); 
inv i5 (sr_5, sr_5n); 
inv i6 (sr_6, sr_6n); 
inv i7 (sr_7, sr_7n); 
inv i8 (inr, inrn);

(* RLOC = "X0Y0", HU_SET = "h0" *) FD sr0 (.C(clk), .D(sr_1n), .Q(sr_0));
(* RLOC = "X0Y0", HU_SET = "h0" *) FD sr1 (.C(clk), .D(sr_2n), .Q(sr_1));
(* RLOC = "X0Y1", HU_SET = "h0" *) FD sr2 (.C(clk), .D(sr_3n), .Q(sr_2));
(* RLOC = "X0Y1", HU_SET = "h0" *) FD sr3 (.C(clk), .D(sr_4n), .Q(sr_3));
(* RLOC = "X0Y0", HU_SET = "h1" *) FD sr4 (.C(clk), .D(sr_5n), .Q(sr_4));
(* RLOC = "X0Y0", HU_SET = "h1" *) FD sr5 (.C(clk), .D(sr_6n), .Q(sr_5));
(* RLOC = "X0Y1", HU_SET = "h1" *) FD sr6 (.C(clk), .D(sr_7n), .Q(sr_6));
(* RLOC = "X0Y1", HU_SET = "h1" *) FD sr7 (.C(clk), .D(inrn), .Q(sr_7));
(* LOC = "SLICE_X0Y0" *) FD inq (.C(clk), .D(d), .Q(inr));
FD outq (.C(clk), .D(sr_0n), .Q(outr)); assign q = outr;
endmodule // ffs

In the preceding example, you will need to specify the KEEP_HIERARCHY property to instances of the ffs module to preserve the hierarchy and define the RPM in the synthesized design:

module top ( 
input clk, 
input d, 
output q
);

wire c1, c2;

(* KEEP_HIERARCHY = "YES" *) ffs u0 (clk, d, c1); 
(* KEEP_HIERARCHY = "YES" *) ffs u1 (clk, c1, c2); 
(* KEEP_HIERARCHY = "YES" *) ffs u2 (clk, c2, q);

endmodule // top

VHDL Syntax

Declare the VHDL attribute as follows:

attribute HU_SET : string;

Specify the VHDL constraint as follows:

attribute HU_SET of {component_name | entity_name | label_name} :
{component|entity|label} is "NAME";

Where,

• {component_name | entity_name | label_name} is the design element.
• {component|entity|label} is the instance ID of the design element.
• "NAME" is the unique set name to give to the HU_SET.

XDC Syntax

The HU_SET property can not be defined using XDC constraints. The HU_SET property, when present on logic elements with the RLOC property, defines relatively placed macros (RPMs), and results in the read-only RPM property in the netlist of synthesized designs.

Tip: You can use the create_macro and update_macro commands to define macro objects in the Vivado Design Suite, that act like RPMs within the design. Refer to the Vivado Design Suite Tcl Command Reference Guide (UG835) for more information on these commands.

Affected Steps

• Design Floorplanning
• Place Design
• Synthesis