CLOCK_LOW_FANOUT - 2024.1 English

Vivado Design Suite Properties Reference Guide (UG912)

Document ID
UG912
Release Date
2024-06-05
Version
2024.1 English

CLOCK_LOW_FANOUT is a boolean property that can be assigned to clocks that have a small number of loads and that should be contained in a single clock region. The property is assigned to clock nets driven by a global clock buffer or a set of flip flops driven by a global clock buffer.

Tip: A global clock buffer is a BUFGCE, BUFGCE_DIV, BUFGCTRL, BUFG_GT, BUFG_PS, or BUFG_HDIO.

When CLOCK_LOW_FANOUT is TRUE on a clock net driven by a global clock buffer, the loads should be contained within a single clock region and be driven by global clock resources. A load is defined as any leaf input pin on the clock network, not only the sequential clock pins. For example, LUT pins are counted as loads. If there are too many loads on the net, the Vivado tool will return a warning and ignore the CLOCK_LOW_FANOUT property.

When CLOCK_LOW_FANOUT is TRUE on a set of flip flops driven by a BUFGCE global clock buffer, the BUFGCE global clock buffer will be replicated and drives only the flip flops with the setting. The flip flops are placed in a single clock region and driven by global clock resources.

The CLOCK_LOW_FANOUT property can conflict with other clock or placement properties. For instance, if CLOCK_DEDICATED_ROUTE is specified on the same net with any value other than TRUE, the CLOCK_DEDICATED_ROUTE property takes precedence and CLOCK_LOW_FANOUT is ignored with a warning, CLOCK_DELAY_GROUP will take precedence over CLOCK_LOW_FANOUT if all of the members of the CLOCK_DELAY_GROUP cannot be placed in a single clock region. USER_CLOCK_ROOT, LOC, and PBLOCK properties can also create conflicts with the CLOCK_LOW_FANOUT property. In each of these cases CLOCK_LOW_FANOUT is ignored and a warning is returned.

Architecture Support
UltraScale and UltraScale+ architectures.
Applicable Objects
  • Clock nets (get_nets) connected to the output of global clock buffers that should be constrained to a single clock region.
  • Flip flop cells (get_cells) connected to the output of a BUFGCE global clock buffer. A new BUFGCE global clock buffer is replicated in parallel with the existing BUFGCE global clock buffer and the loads of the new BUFGCE global clock buffer are constrained to a single clock region.
Value
  • TRUE: The clock is a low fanout net and should be constrained into a single clock region.
  • FALSE: The clock is not a low fanout signal, or should not be constrained to a single clock region (default).

Syntax

Verilog Syntax

Not applicable

VHDL Syntax

Not applicable

XDC Syntax
set_property CLOCK_LOW_FANOUT TRUE [get_nets <clk_nets>] 
set_property CLOCK_LOW_FANOUT TRUE [get_cells <ff_cells>]

Where

  • <clk_nets> is a list of clock nets directly connected to the output of global clock buffers, that are driven by a common cell, such as an MMCM for example.
  • <ff_cells> is a list of flip flop cells directly connect to the output of a BUFGCE global clock buffer.

XDC Syntax Example:

# Define a clock group to reduce skew between the nets.
set_property CLOCK_LOW_FANOUT TRUE [get_nets -of [get_pins block/myBufg/O]]

# Define a list of Flip Flops to be driven by a separate BUFGCE and placed in a single clock region
set_property CLOCK_LOW_FANOUT TRUE [get_cells block/myStartupCircuit/startup_reg[*]]

Affected Steps

  • Opt Design
  • Place Design
  • report_drc