Description
A cell is an instance of a netlist logic object, which can either be a leaf-cell or a hierarchical cell. A leaf-cell is a primitive, or a primitive macro, with no further logic detail in the netlist. A hierarchical cell is a module or block that contains one or more additional levels of logic, and eventually concludes at leaf-cells.
Related Objects
As seen in the figure above, cells have PINs which are connected to NETs to define the external netlist. Hierarchical cells also contain PORTs that are associated with PINs, and which connect internally to NETs to define the internal netlist of the hierarchy.
Leaf CELLs are placed, or mapped, onto device resources on the target AMD FPGA. The CELL can be placed onto a BEL object in the case of basic logic such as flops, LUTs, and MUXes; or can be placed onto a SITE object in the case of larger logic cells such as BRAMs and DSPs. BELs are also collected into larger SITEs, called SLICEs, so a cell can be associated with a BEL and a SITE object. SITEs are grouped into CLOCK_REGIONs and TILEs.
CELLs are also associated with TIMING_PATHs in the design, and can be associated with DRC_VIOLATIONs to help you quickly locate and resolve design issues.
You can query the CELLs associated with pins, timing paths, nets, bels, clock regions, sites, or DRC violations:
get_cells -of [get_nets clk]
Properties
There are different types of leaf-cell objects, defined by the PRIMITIVE_GROUP, PRIMITIVE_SUBGROUP, and PRIMITIVE_TYPE properties as enumerated below.
PRIMITIVE_GROUP | PRIMITIVE_SUBGROUP | PRIMITIVE_TYPE |
---|---|---|
BLOCKRAM | BRAM | BLOCKRAM.BRAM.RAMB18E2 BLOCKRAM.BRAM.RAMB36E2 |
CLB | CARRY | CLB.CARRY.CARRY8 |
LUT | CLB.LUT.LUT1 CLB.LUT.LUT2 CLB.LUT.LUT3 CLB.LUT.LUT4 CLB.LUT.LUT5 CLB.LUT.LUT6 |
|
LUTRAM | CLB.LUTRAM.RAM32M CLB.LUTRAM.RAM32M16 CLB.LUTRAM.RAM32X1D |
|
MUXF | CLB.MUXF.MUXF7 CLB.MUXF.MUXF8 |
|
SRL | CLB.SRL.SRL16E CLB.SRL.SRLC16E CLB.SRL.SRLC32E |
|
Others | CLB.others.LUT6_2 | |
CLOCK | BUFFER | CLOCK.BUFFER.BUFGCE CLOCK.BUFFER.BUFGCE_DIV |
PLL | CLOCK.PLL.MMCME3_ADV CLOCK.PLL.PLLE3_ADV |
|
CONFIGURATION | BSCAN | CONFIGURATION.BSCAN.BSCANE2 |
I/O | BDIR_BUFFER | I/O.BIDIR_BUFFER.IOBUFDS |
BITSLICE | I/O.BITSLICE.BITSLICE_CONTROL I/O.BITSLICE.RIU_OR I/O.BITSLICE.RXTX_BITSLICE I/O.BITSLICE.TX_BITSLICE_TRI |
|
INPUT_BUFFER | I/O.INPUT_BUFFER.HPIO_VREF I/O.INPUT_BUFFER.IBUF I/O.INPUT_BUFFER.IBUFDS |
|
OUTPUT_BUFFER | I/O.OUTPUT_BUFFER.IOBUFE3 I/O.OUTPUT_BUFFER.OBUF I/O.OUTPUT_BUFFER.OBUFDS |
|
OTHERS | others | others.others.others OTHERS.others.AND2B1L OTHERS.others.GND OTHERS.others.VCC |
REGISTER | SDR | REGISTER.SDR.FDCE REGISTER.SDR.FDPE REGISTER.SDR.FDRE REGISTER.SDR.FDSE |
RTL_GATE | buf | RTL_GATE.buf.RTL_INV |
logical | RTL_GATE.logical.RTL_AND RTL_GATE.logical.RTL_OR RTL_GATE.logical.RTL_XOR |
|
RTL_MEMORY | ram | RTL_MEMORY.ram.RTL_RAM |
rom | RTL_MEMORY.rom.RTL_ROM | |
RTL_MUX | mux | RTL_MUX.mux.RTL_MUX |
RTL_OPERATOR | arithmetic | RTL_OPERATOR.arithmetic.RTL_ADD RTL_OPERATOR.arithmetic.RTL_MULT RTL_OPERATOR.arithmetic.RTL_SUB |
equality | RTL_OPERATOR.equality.RTL_EQ | |
shift | RTL_OPERATOR.shift.RTL_RSHIFT | |
REGISTER | flop | RTL_REGISTER.flop.RTL_REG |
All cells have a common set of properties; but each cell GROUP, SUBGROUP, and TYPE can also have unique properties. You can report the properties for specific types of CELL objects by filtering on the PRIMITIVE_GROUP, PRIMITIVE_SUBGROUP or PRIMITIVE_TYPE property value.
PRIMITIVE_TYPE is an enumerated property, the defined values of which can be returned
with the list_property_value
command:
list_property_value -class cell PRIMITIVE_TYPE
However, a design will probably not contain cells for each defined PRIMITIVE_TYPE. The following Tcl code searches hierarchically through a design and returns unique occurrences of the PRIMITIVE_TYPE property for all the cells in the design.
foreach x [get_cells -hierarchical *] {
lappend primTypes [get_property PRIMITIVE_TYPE $x] } join [lsort -unique $primTypes] \n
From the returned list, $primTypes, you can report the properties for a specific PRIMITIVE_TYPE using the following command:
report_property -all [lindex [get_cells -hier -filter {PRIMITIVE_TYPE == <val>}] 0]
Where <val> represents the PRIMITIVE_TYPE of interest. For example, to return the properties of the BLOCKRAM.BRAM.RAM18E2 type cell:
report_property -all [lindex [get_cells -hier -filter {PRIMITIVE_TYPE == "BLOCKRAM.BRAM.RAMB18E2"}] 0]
report_property
command
returns a warning that no objects were found if there are no related objects in the
current design. Refer to the
Vivado
Design Suite Tcl Command Reference Guide (UG835) for more
information on this command.You can also return the properties from a hierarchical cell using the following Tcl command:
report_property -all [lindex [get_cells -hier -filter {!IS_PRIMITIVE}] 0]
Of course, you can also simply return the properties for the specific cell of interest:
report_property -all [get_cells <cell_name>]