The AUTOPIPELINE_MODULE property establishes a separate name-space for all group names defined throughout sub-hierarchies. It must be set on the hierarchy which includes the nets tagged with AUTOPIPELINE_GROUP and AUTOPIPELINE_LIMIT. It also must be used when a module with auto-pipelining properties is instantiated several times in the design. See “Auto-Pipelining” in Vivado Design Suite User Guide: Implementation (UG904) for more information.
Architecture Support
UltraScale, UltraScale+, Versal adaptive SoC.
Applicable Objects
Hierarchical cells.
Value
- <True>
- The auto-pipelining insertion happens in the specified module.
- <False>
- No auto-pipelining insertion happens in the specified module. This is the default mode.
Syntax
- VHDL Example Syntax
-
attribute autopipeline_module : boolean; attribute autopipeline_module of beh: architecture is "true"; - Verilog Example Syntax
-
(* autopipeline_module = “true” *) module test(in1, in2, clk, out1) - XDC Example Syntax
-
set_property AUTOPIPELINE_MODULE TRUE [get_cells test]
Affected Steps
- Place Design
- Phys Opt Design