HW_SIO_GTGROUP - 2024.1 English

Vivado Design Suite Properties Reference Guide (UG912)

Document ID
UG912
Release Date
2024-05-30
Version
2024.1 English

Description

GT groups relate to the GT IO Banks on the hardware device, with the number of available GT pins and banks determined by the target AMD FPGA. On the Kintex 7 xc7k325 part, for example, there are four GT groups, each containing four differential GT pin pairs. Each GT pin has its own receiver, hw_sio_rx, and transmitter, hw_sio_tx. GT groups can also include one shared PLL per quad, or Quad PLL. The GT groups are defined on the IBERT debug core, and can be customized with a number of user settings when the IBERT is added into the RTL design. Refer to the Integrated Bit Error Ratio Tester 7 Series GTX Transceivers LogiCORE IP Product Guide (PG132) for more information.

Related Objects

GT Groups are associated with hw_server, hw_target, hw_device, hw_sio_ibert, hw_sio_gt, hw_sio_common, hw_sio_pll, hw_sio_tx, hw_sio_rx, and hw_sio_link objects.

You can query the GT groups associated with these objects:

get_hw_sio_gtgroups -of [get_hw_sio_gts *MGT_X0Y9]

Properties

You can use the report_property command to report the properties of a HW_SIO_GTGROUP. Refer to the Vivado Design Suite Tcl Command Reference Guide (UG835) for more information. The properties on the hw_sio_gtgroup object include the following, with example values:

Property	Type	Read-only	Visible	Value
CLASS	string	true	true	hw_sio_gtgroup
DISPLAY_NAME	string	true	true	Quad_117
GT_TYPE	string	true	true	7 Series GTX
NAME	string	true	true	
localhost/xilinx_tcf/Digilent/210203327463A/0_1/IBERT/Quad_117 PARENT	string	true	true localhost/xilinx_tcf/Digilent/210203327463A/0_1/IBERT

To report the properties for a specific HW_SIO_GTGROUP, you can copy and paste the following command into the Vivado Design Suite Tcl shell or Tcl Console:

report_property -all [lindex [get_hw_sio_gtgroups] 0]