AUTOPIPELINE_GROUP - 2024.1 English

Vivado Design Suite Properties Reference Guide (UG912)

Document ID
UG912
Release Date
2024-05-30
Version
2024.1 English

The AUTOPIPELINE_GROUP property (see AUTOPIPELINE_MODULE, AUTOPIPELINE_INCLUDE, AUTOPIPELINE_LIMIT) is used to define a group of nets as the objects of auto-pipelining optimization. When this optimization feature is triggered, it will insert and place the additional pipeline stages based on setup timing slack and SLR distance. See “Auto-Pipelining” in Vivado Design Suite User Guide: Implementation (UG904) for more information.

Architecture Support

AMD UltraScale™ , AMD UltraScale+™ , AMD Versal™ architectures.

Applicable Objects

  • Nets (get_nets)
  • Cells (get_cells)

Each single net should be directly driven by a flip-flop, and the fanout load can only be 1.

Value

<group_name>: This is a unique string value that can be assigned to one or more nets. The placer will take the specified objects as one whole group to implement the auto-pipeline insertion. The signals with a same auto-pipeline group name must receive an equal number of auto-inserted pipeline flip-flops.

Syntax

VHDL Example Syntax
attribute autopipeline_group : string; 
signal mywire: std_logic_vector(2 downto 1);
attribute autopipeline_group of mywire: signal is "group_name";
Verilog Example Syntax
(* autopipeline_group="group_name"*)	wire mywire;
XDC Example Syntax
set_property AUTOPIPELINE_GROUP group_name [get_nets mywire]

Affected Steps

  • Place Design
  • Phys Opt Design