Single-ended I/O standards with a differential input buffer require an input reference voltage (VREF). When VREF is required within an I/O bank, you can use the dedicated VREF pin as an external VREF supply, or an internally generated VREF using the INTERNAL_VREF property, or for HP I/O banks on UltraScale devices use the VREF scan accessed through the HPIO_VREF primitive.
The INTERNAL_VREF property specifies the use of an internal regulator on an I/O bank to supply the voltage reference (VREF) for I/O standards requiring a reference voltage. Internally generated reference voltages remove the need to provide a particular VREF through a supply rail on the printed circuit board (PCB). This can reduce routing congestion on the system-level design.
Refer to 7 Series FPGAs SelectIO Resources User Guide (UG471) or to UltraScale Architecture SelectIO Resources User Guide (UG571) for more information.
- Architecture Support
- All architectures.
- Applicable Objects
- I/O Bank (
get_iobanks) - Values
-
- 0.60
- 0.675
- 0.7 (UltraScale only)
- 0.75
- 0.84 (UltraScale only)
- 0.90
Note: Not all values are supported in all types of I/O banks.
Syntax
- Verilog Syntax
-
Not applicable
- VHDL Syntax
-
Not applicable
- XDC Syntax
-
set_property INTERNAL_VREF {value} [get_iobanks bank]Where
valueis the reference voltage value.XDC Syntax Example:
# Designate Bank 14 to have a reference voltage of 0.75 Volts set_property INTERNAL_VREF 0.75 [get_iobanks 14]
Affected Steps
- I/O planning
- Place Design
- DRC
- report_power