CONTROL_SET_REMAP - 2024.1 English

Vivado Design Suite Properties Reference Guide (UG912)

Document ID
UG912
Release Date
2024-05-30
Version
2024.1 English

While all registers support resets and clock enables, their use can significantly affect the end implementation in terms of performance, utilization, and power. Designs with a large number of unique control sets can have fewer options for placement, resulting in higher power and lower performance. The CONTROL_SET_REMAP property is placed on register primitives to trigger a control set reduction on a specific register during logical optimization (opt_design).

When a logic path ends at a fabric register (FD) clock enable, or synchronous set/reset, the property on the register instructs Vivado logic optimization to map the enable or reset signal to the data pin (D), which has a dedicated LUT connection and can be faster. If possible, the logic is combined with an existing LUT driving the D-input to prevent the insertion of extra levels of logic.

Important: This optimization is automatically triggered when the CONTROL_SET_REMAP property is detected on any register. DONT_TOUCH prevents the optimization on specified cells or hierarchy.

For more information on reducing control sets, refer to this link in the UltraFast Design Methodology Guide for FPGAs and SoCs (UG949) for more information.

Architecture Support
All architectures.
Applicable Objects
Cells (get_cells)
Value
ENABLE
Remaps the EN input to the D-input.
RESET
Remaps the synchronous S or R input to the D-input.
ALL
Same as ENABLE and RESET combined.
NONE
Do nothing. This is the default, and is the same as if the property were not set on the cell.

Syntax

Verilog Syntax

Not applicable

VHDL Syntax

Not applicable

XDC Syntax
set_property CONTROL_SET_REMAP <value> [get_cells <cell_pattern>]

XDC Syntax Example

# Specifies control set reduction based on Enable signals 
set_property CONTROL_SET_REMAP ENABLE [get_cells ff*]

Affected Steps

  • Opt Design