EXTRACT_ENABLE - 2024.1 English

Vivado Design Suite Properties Reference Guide (UG912)

Document ID
UG912
Release Date
2024-05-30
Version
2024.1 English

EXTRACT_ENABLE controls whether registers infer enables. Typically, the Vivado tools extract or not extract enables based on heuristics that typically benefit the most amount of designs. In cases where Vivado is not behaving in a desired way, this attribute overrides the default behavior of the tool. If there is an undesired enable going to the CE pin of the flip-flop, this attribute can force it to the D input logic. Conversely, if the tool is not inferring an enable that is specified in the RTL, this attribute can tell the tool to move that enable to the CE pin of the flip-flop.

This is a way for user to indicate on a granular level whether they want enable logic on control path or data path.

Architecture Support
All architectures.
Applicable Objects
The EXTRACT_ENABLE attribute can be placed on the cells, ports and nets.
Values
The enable will go directly to the enable pin (CE) of the register.
FALSE (or NO)
The enable will not go to the enable pin (CE) of the register.

Syntax

Verilog Syntax
(* extract_enable = "yes" *) reg	my_reg;
VHDL Syntax
signal my_reg : std_logic; 
attribute extract_enable : string;
attribute extract_enable of my_reg: signal is "no";
XDC Syntax
set_property EXTRACT_ENABLE yes [get_cells my_reg]

Affected Steps

  • Synthesis