LOCK_PINS - 2024.1 English

Vivado Design Suite Properties Reference Guide (UG912)

Document ID
UG912
Release Date
2024-06-05
Version
2024.1 English

LOCK_PINS is a cell property used to specify the mapping of logical LUT inputs (I0, I1, I2, …) to physical LUT inputs (A6, A5, A4, …) on the AMD FPGA resource. A common use is to force timing-critical LUT inputs to be mapped to the fastest A6 and A5 physical LUT inputs.

By default, LUT pins are mapped in order from highest to lowest. The highest logical pin is mapped to the highest physical pin.

  • ALUT6 placed on an A6LUT bel, would have a default pin mapping of:
    I5:A6 I4:A5 I3:A4 I2:A3 I1:A2 I0:A1
  • A LUT5 placed on a D5LUT bel, would have a default pin mapping of:
    I5:A5 I4:A4 I3:A3 I2:A2 I1:A1
  • A LUT2 placed on an A6LUT bel, would have a default pin mapping of:
    I1:A6 I0:A5

The LOCK_PINS property is used by the Vivado router, which will not modify pin mappings on locked LUTs even if it would result in improved timing. LOCK_PINS is also important for directed routing. If a pin that is connected by a directed route, is swapped with another pin, the directed route will no longer align with the LUT connection, resulting in an error. All LUT cells driven by a directed route net should have their pins locked using LOCK_PINS. Refer to the Vivado Design Suite User Guide: Implementation (UG904) for more information on directed routing.

Note: DONT_TOUCH does not imply LOCK_PINS.

When running the phys_opt_design -critical_pin_opt optimization, a cell with the LOCK_PINS property is not optimized, and the pin mapping specified by LOCK_PINS is retained. Refer to the Vivado Design Suite Tcl Command Reference Guide (UG835) for more information on the phys_opt_design command.

When the LOCK_PINS property is removed from a cell, the pin mapping is cleared and the pins are free to be swapped. However, there is no immediate change to the current pin assignments.

Architecture Support
All architectures.
Applicable Objects
LUT Cells (get_cells)
Values
  • LOCK_PINS {I0:A6 I1:A5}: One or more pin mapping pairs, assigning LUT logical pins to LUT physical pins using logical-to-physical pin map pairs.
    • The LOCK_PINS value syntax is an unordered list of pin mappings, separated by commas in HDL, or by white space in XDC.
    • The list of possible instance pins ranges from I0 for a LUT1, to I0 through I5 for a LUT6. The physical pins range from A6 (fastest) to A1 for a 6LUT and A5 (fastest) to A1 for a 5LUT.
Note: The ISE supported values of ALL, or no value to imply ALL, are not supported in the Vivado Design Suite. To lock ALL pins, each pin must be explicitly specified. Any unlisted logical pins are mapped to a physical pin using the default mapping.

Syntax

Verilog Syntax

LOCK_PINS values can be assigned as a Verilog attribute placed on instantiated LUT cells (e.g. LUT6, LUT5, etc).

The following example defines LOCK_PINS with pin mapping logical I1 to A5, and logical I2 to A6, on a LUT cell LUT_inst_0:

(* LOCK_PINS = "I1:A5, I2:A6" *) LUT6 #(.INIT(64'h1) ) LUT_inst_0 (. . .

Verilog Example:

module top ( i0,
i1,
i2,
i3,
i4,
i5, o0);
input i0; input i1; input i2; input i3; input i4; input i5; output o0;

(* LOCK_PINS = "I1:A5,I2:A6" *) LUT6 #(
.INIT(64'h0000000000000001))
LUT_inst_0 (.I0(i0),
.I1(i1),
 

.I2(i2),
.I3(i3),
.I4(i4),
.I5(i5),
.O(o0));
endmodule
VHDL Syntax

LOCK_PINS values can be assigned as a VHDL attribute placed on instantiated LUT cells (e.g. LUT6, LUT5, etc).

The following example defines LOCK_PINS with pin mapping logical I1 to A5, and logical I2 to A6, on a LUT cell LUT_inst_0:

attribute LOCK_PINS : string;
attribute LOCK_PINS of LUT_inst_0 : label is "I1:A5, I2:A6";
. . .

VHDL Example:

entity top is port (
i0, i1, i2, i3, i4, i5 : in std_logic; o0 : out std_logic
);
end entity top;
architecture struct of top is attribute lock_pins : string;
attribute lock_pins of LUT_inst_0 : label is "I1:A5, I2:A6";

begin
LUT_inst_0 : LUT6 generic map ( INIT => "1"
) port map ( I0 => i0, I1 => i1, I2 => i2, I3 => i3, I4 => i4, I5 => i5, O => o0
);
end architecture struct;
XDC Syntax

The LOCK_PINS property can be set on LUT cells using the set_property Tcl command in the Vivado Design Suite:

set_property LOCK_PINS {pin pairs} [get_cells instance_name]

Where instance_name is one or more LUT cells.

Important: XDC requires white space separation between pin pairs to satisfy the Tcl list syntax, while HDL syntax requires comma-separated values.

XDC Syntax Example:

% set myLUT2	[get_cells u0/u1/i_365]
% set_property LOCK_PINS {I0:A5 I1:A6} $myLUT2
% get_property LOCK_PINS $myLUT2 I0:A5 I1:A6
% reset_property LOCK_PINS $myLUT2
% set myLUT6 [get_cells u0/u1/i_768]
% set_property LOCK_PINS I0:A6 ; # mapping of I1 through I5 are dont-cares

Affected Steps

  • Phys Opt Design
  • Route Design