PROHIBIT - 2024.1 English

Vivado Design Suite Properties Reference Guide (UG912)

Document ID
UG912
Release Date
2024-05-30
Version
2024.1 English

PROHIBIT specifies that a BEL or SITE cannot be used for placement.

Tip: The use of PROHIBIT on RAMB18 sites will not prohibit the placement of a RAMB36. Likewise the use of PROHIBIT on RAMB36 sites will not prohibit the placement of the RAMB18.
Architecture Support
All architectures.
Applicable Objects
  • SITEs (get_sites)
  • BELs (get_bels)
Values
TRUE (or 1): Prohibit the specified BEL or SITE from use during placement.

Syntax

Verilog Syntax

Not applicable

VHDL Syntax

Not applicable

XDC Syntax
set_property PROHIBIT 1 [get_sites site]

XDC Syntax Example

# Prohibit the use of package pin Y32 
set_property prohibit 1 [get_sites Y32]

Affected Steps

  • I/O planning
  • Place Design